[Mesa-dev] [PATCH 1/2] radv: fix setting CB_DCC_BASE if the base level doesn't enable DCC

[Samuel Pitoiset]

CB_DCC_BASE should be 0 if no DCC.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
---
 src/amd/vulkan/radv_device.c | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 26b31cff9f1..dc5de683050 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -4342,15 +4342,16 @@ radv_initialise_color_surface(struct radv_device *device,
 	va += iview->image->cmask.offset;
 	cb->cb_color_cmask = va >> 8;
 
-	va = radv_buffer_get_va(iview->bo) + iview->image->offset;
-	va += iview->image->dcc_offset;
+	if (radv_dcc_enabled(iview->image, iview->base_mip)) {
+		va = radv_buffer_get_va(iview->bo) + iview->image->offset;
+		va += iview->image->dcc_offset;
 
-	if (radv_dcc_enabled(iview->image, iview->base_mip) &&
-	    device->physical_device->rad_info.chip_class <= GFX8)
-		va += plane->surface.u.legacy.level[iview->base_mip].dcc_offset;
+		if (device->physical_device->rad_info.chip_class <= GFX8)
+			va += plane->surface.u.legacy.level[iview->base_mip].dcc_offset;
 
-	cb->cb_dcc_base = va >> 8;
-	cb->cb_dcc_base |= surf->tile_swizzle;
+		cb->cb_dcc_base = va >> 8;
+		cb->cb_dcc_base |= surf->tile_swizzle;
+	}
 
 	uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
 	cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
-- 
2.22.0