[Openchrome-devel] openchrome 0.6.0 regressions on VX900 laptop
Xavier Bachelot
xavier at bachelot.org
Tue Mar 14 22:24:36 UTC 2017
Hi Kevin,
On 14/03/2017 22:33, Kevin Brace wrote:
> Hi Xavier,
>
> Okay, at least some progress.
> I was guessing that LVDS1 was still at IGA1, so switching to IGA2 will correct the problem, but I guess there were still some missing pieces.
> Based on what you reported, I wrote a patch that should now correctly initialize LVDS1 for VX855 and VX900 chipsets.
> It appears that these only have one LVDS channel as opposed to CX700/VX700 and VX800 chipsets which appear to have two LVDS channels, to which one of them can be used as DVI.
> I hope the patch works.
>
Thanks for the patch. It may or may not work, I can't tell, as both LVDS
channels are powered down and thus the screen is black.
I've attached the X log and regs dump.
btw, I don't know if you're used to irc but I'm on #openchrome on
freenode. Might be easier to debug this.
Regards,
Xavier
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via-chrome-tool (C) 2009 by VIA Technologies, Inc.
This is FREE SOFTWARE with ABSOLUTELY NO WARRANTY
Sequencer register dump (IO Port address: 0x3c4):
3c5.00 = 0x03 (Reset)
3c5.01 = 0x01 (Clocking Mode)
3c5.02 = 0x0f (Map Mask)
3c5.03 = 0x00 (Character Map Select)
3c5.04 = 0x0e (Memory Mode)
3c5.10 = 0x01 (Extended Register Unlock)
3c5.11 = 0x78 (Configuration 0)
3c5.12 = 0x00 (Configuration 1)
3c5.13 = 0x00 (Configuration 2 (DVP1 strapping))
3c5.14 = 0x00 (Frame Buffer Size Control)
3c5.15 = 0x22 (Display Mode Control)
3c5.16 = 0x0c (Display FIFO Threshold Control)
3c5.17 = 0x1f (Display FIFO Control)
3c5.18 = 0x70 (Display Arbiter Control 0)
3c5.19 = 0x7f (Power Management)
0x01 CPU Interface Clock Control: 0x01
0x02 Display Interface Clock Control: 0x02
0x04 MC Interface Clock Control: 0x04
0x08 Typical Arbiter Interface Clock Control: 0x08
0x10 AGP Interface Clock Control: 0x10
0x20 P-Arbiter Interface Clock Control: 0x20
0x40 MIU/AGP Interface Clock Control: 0x40
3c5.1a = 0x88 (PCI Bus Control)
0x01 LUT Shadow Access: 0x00
0x04 PCI Burst Write Wait State Select (0: 0 Wait state, 1: 1 Wait state): 0x00
0x08 Extended Mode Memory Access Enable (0: Disable, 1: Enable): 0x08
0x40 Software Reset (0: Default value, 1: Reset): 0x00
0x80 Read Cache Enable (0: Disable, 1: Enable): 0x80
3c5.1b = 0xf0 (Power Management Control 0)
0x01 Primary Display's LUT Off: 0x00
0x18 Primary Display Engine VCK Gating: 0x10
0x60 Secondary Display Engine LCK Gating: 0x60
3c5.1c = 0x54 (Horizontal Display Fetch Count Data)
3c5.1d = 0x00 (Horizontal Display Fetch Count Control)
3c5.1e = 0x01 (Power Management Control)
0x01 ROC ECK: 0x01
0x02 Replace ECK by MCK: 0x00
0x08 Spread Spectrum: 0x00
0x30 DVP1 Power Control: 0x00
0xc0 VCP Power Control: 0x00
3c5.20 = 0x00 (Typical Arbiter Control 0)
3c5.21 = 0x18 (Typical Arbiter Control 1)
3c5.22 = 0x14 (Display Arbiter Control 1)
3c5.26 = 0x3d (IIC Serial Port Control 0)
3c5.2a = 0x00 (Power Management Control 5)
0x03 LVDS Channel 1 Pad Control: 0x00
0x0c LVDS Channel 2 Pad Control: 0x00
0x40 Spread Spectrum Type FIFO: 0x00
3c5.2b = 0x01 (LVDS Interrupt Control)
0x01 MSI Pending IRQ Re-trigger: 0x01
0x02 CRT Hot Plug Detect Enable: 0x00
0x04 CRT Sense IRQ status: 0x00
0x08 CRT Sense IRQ enable: 0x00
0x10 LVDS Sense IRQ status: 0x00
0x20 LVDS Sense IRQ enable: 0x00
3c5.2c = 0xdc (General Purpose I/O Port)
3c5.2d = 0x3f (Power Management Control 1)
0x03 ECK Pll Power Control: 0x03
0x0c LCK PLL Power Control: 0x0c
0x30 VCK PLL Power Control: 0x30
0xc0 E3_ECK_N Selection: 0x00
3c5.2e = 0xfb (Power Management Control 2)
0x03 Video Playback Engine V3/V4 Gated Clock VCK: 0x03
0x0c PCI Master / DMA Gated Clock ECK/CPUCK: 0x08
0x30 Video Processor Gated Clock ECK: 0x30
0xc0 Capturer Gated Clock ECK: 0xc0
3c5.31 = 0x3d (IIC Serial Port Control 1)
3c5.35 = 0x5b (Subsystem Vendor ID Low)
3c5.36 = 0x10 (Subsystem Vendor ID High)
3c5.37 = 0xfd (Subsystem ID Low)
3c5.38 = 0x0c (Subsystem ID High)
3c5.39 = 0x40 (BIOS Reserved Register 0)
3c5.3a = 0x00 (BIOS Reserved Register 1)
3c5.3b = 0x03 (PCI Revision ID Back Door)
3c5.3c = 0x1d (Miscellaneous)
0x01 AGP Bus Pack Door AGP3 Enable: 0x01
0x02 Switch 3 PLLs to Prime Output: 0x00
0x04 LCDCK PLL Locked Detect: 0x04
0x08 VCK PLL Locked Detect: 0x08
0x10 ECL PLL Locked Detect: 0x10
0x60 PLL Frequency Division Select for Testing: 0x00
3c5.3d = 0x0c (General Purpose I/O Port)
3c5.3e = 0x00 (Miscellaneous Register for AGP Mux)
3c5.3f = 0xff (Power Management Control 2)
0x03 Video Clock Control (Gated ECK): 0x03
0x0c 2D Clock Control (Gated ECK/CPUCK): 0x0c
0x30 3D Clock Control (Gated ECK): 0x30
0xc0 CR Clock Control (Gated ECK): 0xc0
3c5.40 = 0x08 (PLL Control)
0x01 Reset ECK PLL: 0x00
0x02 Reset VCK PLL: 0x00
0x04 Reset LCDCK PLL: 0x00
0x08 LVDS Interrupt Method: 0x08
0x30 Free Run ECK Frequency within Idle Mode: 0x00
0x80 CRT Sense Enable: 0x00
3c5.41 = 0x40 (Typical Arbiter Control 1)
3c5.42 = 0x30 (Typical Arbiter Control 2)
3c5.43 = 0x7d (Graphics Bonding Option)
0x01 Notebook Used Flag: 0x01
0x04 Typical Channel 1 Arbiter Read Back Data Overwrite Flag: 0x04
0x08 Typical Channel 0 Arbiter Read Back Data Overwrite Flag: 0x08
0x10 IGA1 Display FIFO Underflow Flag: 0x10
0x20 IGA2 Display FIFO Underflow Flag: 0x20
0x40 Windows Media Video Enable Flag: 0x40
0x80 Advance Video Enable Flag: 0x00
3c5.44 = 0xd2 (VCK Clock Synthesizer Value 0)
3c5.45 = 0x0c (VCK Clock Synthesizer Value 1)
3c5.46 = 0x05 (VCK Clock Synthesizer Value 2)
3c5.47 = 0x54 (ECK Clock Synthesizer Value 0)
3c5.48 = 0x80 (ECK Clock Synthesizer Value 1)
3c5.49 = 0x03 (ECK Clock Synthesizer Value 2)
3c5.4a = 0x77 (LDCK Clock Synthesizer Value 0)
3c5.4b = 0x88 (LDCK Clock Synthesizer Value 1)
3c5.4c = 0x05 (LDCK Clock Synthesizer Value 2)
3c5.4d = 0x30 (Preemptive Arbiter Control)
3c5.4e = 0x00 (Software Reset Control)
0x01 HQV/Video/Capture Engine Reset: 0x00
0x02 HQV/Video/Capture Register Reset: 0x00
0x04 2D Engine Reset: 0x00
0x08 2D Register Reset: 0x00
0x10 3D Engine Reset: 0x00
0x20 3D Register Reset: 0x00
0x40 CR Engine Reset: 0x00
0x80 CR Register Reset: 0x00
3c5.4f = 0x5f (CR Gating Clock Control)
3c5.50 = 0x1f (AGP Control)
3c5.51 = 0x00 (Display FIFO Control 1)
3c5.52 = 0x00 (Integrated TV Shadow Register Control)
3c5.53 = 0xff (DAC Sense Control 1)
3c5.54 = 0x00 (DAC Sense Control 2)
3c5.55 = 0x00 (DAC Sense Control 3)
3c5.56 = 0xff (DAC Sense Control 4)
3c5.57 = 0x00 (Display FIFO Control 2)
3c5.58 = 0x06 (GFX Power Control 1)
3c5.59 = 0xdf (GFX Power Control 2)
0x01 GFX-NM AGP Dynamic Clock Enable: 0x01
0x02 GFX-NM GMINT Channel 0 Dynamic Clock Enable: 0x02
0x04 GFX-NM GMINT Channel 1 Dynamic Clock Enable: 0x04
0x08 GFX-NM PCIC Dynamic Clock Enable: 0x08
0x10 GFX-NM IGA Dynamic Clock Enable: 0x10
0x20 IGA Low Threshold Enable: 0x00
0x80 IGA1 Enable: 0x80
3c5.5a = 0x00 (PCI Bus Control 2)
3c5.5b = 0x00 (Device Used Status 0)
0x01 LVDS1 Used IGA2 Source: 0x00
0x02 LBDS1 Used IGA1 Source: 0x00
0x04 LVDS0 Used IGA2 Source: 0x00
0x08 LVDS1 Used IGA1 Source: 0x00
0x10 DAC0 Used IGA2 Source: 0x00
0x20 DAC0 Used IGA1 Source: 0x00
0x40 DAC0 User is TV: 0x00
0x80 DCVI Source Selection is TV: 0x00
3c5.5c = 0x20 (Device Used Status 1)
0x01 DVP1 Used IGA2 Source: 0x00
0x02 DVP1 Used IGA1 Source: 0x00
0x10 DAC1 Used IGA2 Source: 0x00
0x20 DAC1 Used IGA1 Source: 0x20
0x40 DAC1 User is TV: 0x00
3c5.5d = 0xf0 (Timer Control)
3c5.5e = 0x00 (DAC Control 2)
3c5.60 = 0x00 (I2C Mode Control)
3c5.61 = 0x00 (I2C Host Address)
3c5.62 = 0x00 (I2C Host Data)
3c5.63 = 0x40 (I2C Host Control)
3c5.64 = 0x20 (I2C Status)
3c5.65 = 0x00 (Power Management Control 6)
3c5.66 = 0x20 (GTI Control 0)
3c5.67 = 0x20 (GTI Control 1)
3c5.68 = 0x80 (GTI Control 2)
3c5.69 = 0x20 (GTI Control 3)
3c5.6a = 0x00 (GTI Control 4)
3c5.6b = 0x00 (GTI Control 5)
3c5.6c = 0x00 (GTI Control 6)
3c5.6d = 0x80 (GTI Control 7)
3c5.6e = 0x03 (GTI Control 8)
3c5.6f = 0x00 (GTI Control 9)
3c5.70 = 0x20 (GARB Control 0)
3c5.71 = 0x00 (Typical Arbiter Control 2)
3c5.72 = 0x0f (Typical Arbiter Control 3)
3c5.73 = 0x00 (Typical Arbiter Control 4)
3c5.74 = 0x1f (Typical Arbiter Control 5)
3c5.75 = 0x1f (Typical Arbiter Control 6)
3c5.76 = 0x00 (Backlight Control 1)
0x01 Backlight Control Enable: 0x00
3c5.77 = 0x00 (Backlight Control 2)
3c5.78 = 0x86 (Backlight Control 3)
Graphic Controller register dump (IO Port address: 0x3ce):
3cf.00 = 0x00 (Set / Reset)
3cf.01 = 0x00 (Enable Set / Reset)
3cf.02 = 0x00 (Color Compare)
3cf.03 = 0x00 (Data Rotate)
3cf.04 = 0x00 (Read Map Select)
3cf.05 = 0x40 (Mode)
3cf.06 = 0x05 (Miscellaneous)
3cf.07 = 0x0f (Color Don't Care)
3cf.08 = 0xff (Bit Mask)
3cf.20 = 0x00 (Offset Register Control)
3cf.21 = 0x00 (Offset Register A)
3cf.22 = 0x00 (Offset Register B)
CRT controller register dump (IO Port address: 0x3d4):
3d5.00 = 0xbe (Horizontal Total)
3d5.01 = 0xaa (Horizontal Display End)
3d5.02 = 0xaa (Start Horizontal Blank)
3d5.03 = 0x82 (End Horizontal Blank)
3d5.04 = 0xae (Start Horizontal Retrace)
3d5.05 = 0x16 (End Horizontal Retrace)
3d5.06 = 0x25 (Vertical Total)
3d5.07 = 0xb7 (Overflow)
3d5.08 = 0x00 (Preset Row Scan)
3d5.09 = 0x6f (Max Scan Line)
3d5.0a = 0x0d (Cursor Start)
3d5.0b = 0x0e (Cursor End)
3d5.0c = 0x00 (Start Address High)
3d5.0d = 0x00 (Start Address Low)
3d5.0e = 0x1f (Cursor Location High)
3d5.0f = 0x40 (Cursor Location Low)
3d5.10 = 0x01 (Vertical Retrace Start)
3d5.11 = 0x6d (Vertical Retrace End)
3d5.12 = 0x8f (Vertical Display End)
3d5.13 = 0x28 (Offset)
3d5.14 = 0x1f (Underline Location)
3d5.15 = 0xff (Start Vertical Blank)
3d5.16 = 0x26 (End Vertical Blank)
3d5.17 = 0xa3 (CRTC Mode Control)
3d5.18 = 0xff (Line Compare)
3d5.30 = 0x08 (Display Fetch Blocking Control)
3d5.31 = 0x00 (Half Line Position)
3d5.32 = 0x11 (Mode Control)
0x01 Real-Time Flipping: 0x01
0x02 Digital Video Port (DVP) Grammar Correction: 0x00
0x04 Display End Blanking Enable: 0x00
0x08 CRT SYNC Driving Selection (0: Low, 1: High): 0x00
0xe0 HSYNC Delay Number by VCLK: 0x00
3d5.33 = 0x25 (Hsync Adjuster)
3d5.34 = 0x00 (Starting Address Overflow, Bits [23:16])
3d5.35 = 0x00 (Extended Overflow)
3d5.36 = 0x31 (Power Management Control 3)
3d5.37 = 0x34 (DAC Control)
3d5.38 = 0x24 (Signature Data B0)
3d5.39 = 0x17 (Signature Data B1)
3d5.3a = 0x52 (Signature Data B2)
3d5.3b = 0x03 (Scratch Pad 2)
3d5.3c = 0x08 (Scratch Pad 3)
3d5.3d = 0xa4 (Scratch Pad 4)
3d5.3e = 0x00 (Scratch Pad 5)
3d5.3f = 0x0a (Scratch Pad 6)
3d5.40 = 0x00 (Test Mode Control 0)
3d5.43 = 0x90 (IGA1 Display Control)
3d5.45 = 0x01 (Power Now Indicator Control 3)
3d5.46 = 0x00 (Test Mode Control 1)
3d5.47 = 0x04 (Test Mode Control 2)
3d5.48 = 0x00 (Starting Address Overflow)
3d5.50 = 0xf7 (Second CRTC Horizontal Total Period)
3d5.51 = 0x57 (Second CRTC Horizontal Active Data Period)
3d5.52 = 0x57 (Second CRTC Horizontal Blanking Start)
3d5.53 = 0xf7 (Second CRTC Horizontal Blanking End)
3d5.54 = 0x75 (Second CRTC Horizontal Blanking Overflow)
3d5.55 = 0x56 (Second CRTC Horizontal Period Overflow)
3d5.56 = 0xa0 (Second CRTC Horizontal Retrace Start)
3d5.57 = 0x27 (Second CRTC Horizontal Retrace End)
3d5.58 = 0x1d (Second CRTC Vertical Total Period)
3d5.59 = 0xff (Second CRTC Vertical Active Data Period)
3d5.5a = 0xff (Second CRTC Vertical Blanking Start)
3d5.5b = 0x1d (Second CRTC Vertical Blanking End)
3d5.5c = 0x9a (Second CRTC Vertical Blanking Overflow)
3d5.5d = 0x13 (Second CRTC Vertical Period Overflow)
3d5.5e = 0x03 (Second CRTC Vertical Retrace Start)
3d5.5f = 0x6c (Second CRTC Vertical Retrace End)
3d5.60 = 0x13 (Second CRTC Vertical Status 1)
3d5.61 = 0x42 (Second CRTC Vertical Status 2)
3d5.62 = 0x00 (Second Display Starting Address Low)
3d5.63 = 0x00 (Second Display Starting Address Middle)
3d5.64 = 0xac (Second Display Starting Address High)
3d5.65 = 0x56 (Second Display Horizontal Quadword Count)
3d5.66 = 0xac (Second Display Horizontal Offset)
3d5.67 = 0xc6 (Second Display Color Depth and Horizontal Overflow)
3d5.68 = 0x78 (Second Display Queue Depth and Read Threshold)
3d5.69 = 0x00 (Second Display Interrupt Enable and Status)
3d5.6a = 0xc0 (Second Display Channel and LCD Enable)
3d5.6b = 0x00 (Channel 1 and 2 Clock Mode Selection)
3d5.6c = 0x00 (TV Clock Control)
3d5.6d = 0xbe (Horizontal Total Shadow)
3d5.6e = 0xc2 (End Horizontal Blanking Shadow)
3d5.6f = 0x25 (Vertical Total Shadow)
3d5.70 = 0xff (Vertical Display Enable End Shadow)
3d5.71 = 0xa3 (Vertical Display Overflow Shadow)
3d5.72 = 0xff (Start Vertical Blank Shadow)
3d5.73 = 0x26 (End Vertical Blank Shadow)
3d5.74 = 0x23 (Vertical Blank Overflow Shadow)
3d5.75 = 0x02 (Vertical Retrace Start Shadow)
3d5.76 = 0x3e (Vertical Retrace End Shadow)
3d5.77 = 0xde (LCD Horizontal Scaling Factor)
3d5.78 = 0x15 (LCD Vertical Scaling Factor)
3d5.79 = 0x9e (LCD Scaling Control)
3d5.7a = 0x0b (LCD Scaling Parameter 1)
3d5.7b = 0x0b (LCD Scaling Parameter 2)
3d5.7c = 0x19 (LCD Scaling Parameter 3)
3d5.7d = 0x0a (LCD Scaling Parameter 4)
3d5.7e = 0x0a (LCD Scaling Parameter 5)
3d5.7f = 0x0b (LCD Scaling Parameter 6)
3d5.80 = 0x0a (LCD Scaling Parameter 7)
3d5.81 = 0x0b (LCD Scaling Parameter 8)
3d5.82 = 0x0f (LCD Scaling Parameter 9)
3d5.83 = 0x0e (LCD Scaling Parameter 10)
3d5.84 = 0x0a (LCD Scaling Parameter 11)
3d5.85 = 0x0a (LCD Scaling Parameter 12)
3d5.86 = 0x0b (LCD Scaling Parameter 13)
3d5.87 = 0x0e (LCD Scaling Parameter 14)
3d5.88 = 0xe1 (LCD Panel Type)
3d5.8a = 0x01 (LCD Timing Control 1)
3d5.8b = 0xd4 (LCD Power Sequence Control 0)
3d5.8c = 0x2b (LCD Power Sequence Control 1)
3d5.8d = 0x00 (LCD Power Sequence Control 2)
3d5.8e = 0xb5 (LCD Power Sequence Control 3)
3d5.8f = 0x06 (LCD Power Sequence Control 4)
3d5.90 = 0x10 (LCD Power Sequence Control 5)
3d5.91 = 0xc0 (Software Control Power Sequence)
3d5.92 = 0x0f (Read Threshold 2)
3d5.94 = 0x88 (Expire Number and Display Queue Extend)
3d5.95 = 0x22 (Extend Threshold Bit)
3d5.97 = 0x00 (LVDS Channel 2 Function Select 0)
3d5.98 = 0x00 (LVDS Channel 2 Function Select 1)
3d5.99 = 0x11 (LVDS Channel 1 Function Select 0)
3d5.9a = 0x00 (LVDS Channel 1 Function Select 1)
3d5.9b = 0x00 (Digital Video Port 1 Function Select 0)
3d5.9c = 0x00 (Digital Video Port 1 Function Select 1)
3d5.9d = 0x00 (Power Now Control 2)
3d5.9e = 0x00 (Power Now Control 3)
3d5.9f = 0x03 (Power Now Control 4)
3d5.a0 = 0x00 (Horizontal Scaling Initial Value)
3d5.a1 = 0x00 (Vertical Scaling Initial Value)
3d5.a2 = 0x00 (Horizontal and Vertical Scaling Enable)
3d5.a3 = 0x02 (Second Display Starting Address Extended)
3d5.a5 = 0xff (Second LCD Vertical Scaling Factor)
3d5.a6 = 0xff (Second LCD Vertical Scaling Factor)
3d5.a7 = 0x8b (Expected IGA1 Vertical Display End)
3d5.a8 = 0x01 (Expected IGA1 Vertical Display End)
3d5.a9 = 0x00 (Hardware Gamma Control)
3d5.aa = 0x00 (FIFO Depth + Threshold Overflow)
3d5.ab = 0x00 (IGA2 Interlace Half Line)
3d5.ac = 0x00 (IGA2 Interlace Half Line)
3d5.af = 0x00 (P-Arbiter Write Expired Number)
3d5.b0 = 0x00 (IGA2 Pack Circuit Request Threshold)
3d5.b1 = 0x00 (IGA2 Pack Circuit Request High Threshold)
3d5.b2 = 0x00 (IGA2 Pack Circuit Request Expire Threshold)
3d5.b3 = 0x00 (IGA2 Pack Circuit Control)
3d5.b4 = 0x00 (IGA2 Pack Circuit Target Base Address 0)
3d5.b5 = 0x00 (IGA2 Pack Circuit Target Base Address 0)
3d5.b6 = 0x00 (IGA2 Pack Circuit Target Base Address 0)
3d5.b7 = 0x00 (IGA2 Pack Circuit Target Base Address 0)
3d5.b8 = 0x00 (IGA2 Pack Circuit Target Line Pitch)
3d5.b9 = 0x00 (IGA2 Pack Circuit Target Line Pitch)
3d5.ba = 0x00 (V Counter Set Pointer)
3d5.bb = 0x00 (V Counter Set Pointer)
3d5.bc = 0x00 (V Counter Reset Value)
3d5.bd = 0x00 (V Counter Reset Value)
3d5.be = 0x00 (Frame Buffer Limit Value)
3d5.bf = 0x00 (Frame Buffer Limit Value)
3d5.c0 = 0x00 (Expected IGA1 Vertical Display End 1)
3d5.c1 = 0x00 (Expected IGA1 Vertical Display End 1)
3d5.c2 = 0x00 (Third LCD Vertical Scaling Factor)
3d5.c3 = 0x00 (Third LCD Vertical Scaling Factor)
3d5.c4 = 0x00 (Expected IGA1 Vertical Display End 2)
3d5.c5 = 0x00 (Expected IGA1 Vertical Display End 2)
3d5.c7 = 0x00 (Fourth LCD Vertical Scaling Factor)
3d5.c8 = 0x00 (IGA2 Pack Circuit Target Base Address 1)
3d5.c9 = 0x00 (IGA2 Pack Circuit Target Base Address 1)
3d5.ca = 0x00 (IGA2 Pack Circuit Target Base Address 1)
3d5.cb = 0x00 (IGA2 Pack Circuit Target Base Address 1)
3d5.d0 = 0x10 (LVDS PLL1 Control)
3d5.d1 = 0x00 (LVDS PLL2 Control)
3d5.d2 = 0xcb (LVDS Control)
3d5.d3 = 0xc0 (LVDS Second Power Sequence Control 0)
3d5.d4 = 0x00 (LVDS Second Power Sequence Control 1)
3d5.d5 = 0x88 (LVDS Texting Mode Control)
3d5.d6 = 0x00 (DCVI Control Register 0)
3d5.d7 = 0x00 (DCVI Control Register 1)
3d5.d9 = 0x00 (Scaling Down Source Data Offset Control)
3d5.da = 0x00 (Scaling Down Source Data Offset Control)
3d5.db = 0x00 (Scaling Down Source Data Offset Control)
3d5.dc = 0x00 (Scaling Down Vertical Scale Control)
3d5.dd = 0x00 (Scaling Down Vertical Scale Control)
3d5.de = 0x00 (Scaling Down Vertical Scale Control)
3d5.df = 0x00 (Scaling Down Vertical Scale Control)
3d5.e0 = 0x00 (Scaling Down Destination FB Starting Addr 0)
3d5.e1 = 0x00 (Scaling Down Destination FB Starting Addr 0)
3d5.e2 = 0x00 (Scaling Down Destination FB Starting Addr 0)
3d5.e3 = 0x00 (Scaling Down Destination FB Starting Addr 0)
3d5.e4 = 0x00 (Scaling Down SW Source FB Stride)
3d5.e5 = 0x00 (Scaling Down Destination FB Starting Addr 1)
3d5.e6 = 0x00 (Scaling Down Destination FB Starting Addr 1)
3d5.e7 = 0x00 (Scaling Down Destination FB Starting Addr 1)
3d5.e8 = 0x40 (Scaling Down Destination FB Starting Addr 1)
3d5.e9 = 0x00 (Scaling Down Destination FB Starting Addr 2)
3d5.ea = 0x00 (Scaling Down Destination FB Starting Addr 2)
3d5.eb = 0x00 (Scaling Down Destination FB Starting Addr 2)
3d5.ec = 0x00 (IGA1 Down Scaling Destination Control)
3d5.f0 = 0x00 (Snapshot Mode - Starting Address of Disp Data)
3d5.f1 = 0x00 (Snapshot Mode - Starting Address of Disp Data)
3d5.f2 = 0x00 (Snapshot Mode - Starting Address of Disp Data)
3d5.f3 = 0x12 (Snapshot Mode Control)
3d5.f4 = 0x00 (Snapshot Mode Control)
3d5.f5 = 0x00 (Snapshot Mode Control)
3d5.f6 = 0x00 (Snapshot Mode Control)
VCK PLL: dm=210, dtx=2, dr=1, dn=2 VCK Fvco=758854 kHz, Fout=379427 kHz
ECK PLL: dm=596, dtx=2, dr=0, dn=1 ECK Fvco=2854054 kHz, Fout=0 kHz
LDCK PLL: dm=631, dtx=2, dr=1, dn=2 LDCK Fvco=2265823 kHz, Fout=1132911 kHz
SL in System memory: 0x10000000, RTSF in SL: 0x0
Primary Display:
H total=1560, active=1368, blank (1368-536), sync(1392-176)
V total=807, active=400, blank (768-39), sync(769-13)
base_addr=0x00000000, bpp=8
Secondary Display:
H total=1784, active=1368, blank (1368-1784), sync(1440-39)
V total=798, active=768, blank (768-798), sync(771-12)
base_addr=0x0ab00000, bpp=32
Panel Scaling disabled
LVDS Seq Mode: LVDS1 + LVDS2
LVDS CRT Mode: LVDS1 + LVDS2
LVDS Channel 1 Format OpenLDI, Power Down
LVDS Channel 2 Format OpenLDI, Power Down
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[ 75.162]
X.Org X Server 1.18.4
Release Date: 2016-07-19
[ 75.162] X Protocol Version 11, Revision 0
[ 75.162] Build Operating System: 4.7.9-200.fc24.x86_64
[ 75.162] Current Operating System: Linux sam 4.7.2-201.fc24.x86_64 #1 SMP Fri Aug 26 15:58:40 UTC 2016 x86_64
[ 75.163] Kernel command line: BOOT_IMAGE=/vmlinuz-4.7.2-201.fc24.x86_64 root=/dev/mapper/Volume00-root ro rd.md=0 rd.lvm.lv=Volume00/usr KEYTABLE=us SYSFONT=latarcyrheb-sun16 rd.luks=0 rd.lvm.lv=Volume00/root rd.dm=0 rd.lvm.lv=Volume00/swap LANG=en_US.UTF-8 drm.debug=255 via.modeset=1
[ 75.163] Build Date: 15 November 2016 04:39:46AM
[ 75.163] Build ID: xorg-x11-server 1.18.4-5.fc24
[ 75.163] Current version of pixman: 0.34.0
[ 75.163] Before reporting problems, check http://wiki.x.org
to make sure that you have the latest version.
[ 75.163] Markers: (--) probed, (**) from config file, (==) default setting,
(++) from command line, (!!) notice, (II) informational,
(WW) warning, (EE) error, (NI) not implemented, (??) unknown.
[ 75.163] (==) Log file: "/var/log/Xorg.0.log", Time: Tue Mar 14 22:58:25 2017
[ 75.164] (==) Using config directory: "/etc/X11/xorg.conf.d"
[ 75.164] (==) Using system config directory "/usr/share/X11/xorg.conf.d"
[ 75.165] (==) No Layout section. Using the first Screen section.
[ 75.165] (==) No screen section available. Using defaults.
[ 75.165] (**) |-->Screen "Default Screen Section" (0)
[ 75.165] (**) | |-->Monitor "<default monitor>"
[ 75.165] (==) No device specified for screen "Default Screen Section".
Using the first device section listed.
[ 75.165] (**) | |-->Device "Card0"
[ 75.165] (==) No monitor specified for screen "Default Screen Section".
Using a default monitor configuration.
[ 75.165] (==) Automatically adding devices
[ 75.165] (==) Automatically enabling devices
[ 75.165] (==) Automatically adding GPU devices
[ 75.165] (==) Max clients allowed: 256, resource mask: 0x1fffff
[ 75.165] (==) FontPath set to:
catalogue:/etc/X11/fontpath.d,
built-ins
[ 75.165] (==) ModulePath set to "/usr/lib64/xorg/modules"
[ 75.165] (II) The server relies on udev to provide the list of input devices.
If no devices become available, reconfigure udev or disable AutoAddDevices.
[ 75.165] (II) Loader magic: 0x824dc0
[ 75.165] (II) Module ABI versions:
[ 75.165] X.Org ANSI C Emulation: 0.4
[ 75.165] X.Org Video Driver: 20.0
[ 75.165] X.Org XInput driver : 22.1
[ 75.165] X.Org Server Extension : 9.0
[ 75.170] (++) using VT number 1
[ 75.170] (II) systemd-logind: logind integration requires -keeptty and -keeptty was not provided, disabling logind integration
[ 75.175] (--) PCI:*(0:0:1:0) 1106:7122:105b:0cfd rev 0, Mem @ 0xfc000000/16777216, 0xfb000000/16777216, 0xd0000000/268435456, BIOS @ 0x????????/131072
[ 75.175] (II) LoadModule: "glx"
[ 75.175] (II) Loading /usr/lib64/xorg/modules/extensions/libglx.so
[ 75.183] (II) Module glx: vendor="X.Org Foundation"
[ 75.183] compiled for 1.18.4, module version = 1.0.0
[ 75.183] ABI class: X.Org Server Extension, version 9.0
[ 75.183] (==) AIGLX enabled
[ 75.183] (II) LoadModule: "openchrome"
[ 75.184] (II) Loading /usr/lib64/xorg/modules/drivers/openchrome_drv.so
[ 75.184] (II) Module openchrome: vendor="https://www.freedesktop.org/wiki/Openchrome/"
[ 75.184] compiled for 1.18.4, module version = 0.6.0
[ 75.184] Module class: X.Org Video Driver
[ 75.184] ABI class: X.Org Video Driver, version 20.0
[ 75.184] (II) OPENCHROME: Driver for VIA Chrome chipsets: CLE266,
KM400 / KM400A / KN400 / P4M800, K8M800 / K8N800,
PM800 / PN800 / PM880 / CN333 / CN400, P4M800 Pro / VN800 / CN700,
CX700 / VX700, P4M890 / VN890 / CN800, K8M890 / K8N890,
P4M900 / VN896 / CN896, VX800 / VX820, VX855 / VX875, VX900
[ 75.186] (!!) VIA Technologies does not support this driver in any way.
[ 75.186] (!!) For support, please refer to https://www.freedesktop.org/wiki/Openchrome/.
[ 75.186] (!!) (development build, branch master at revision 4936930)
[ 75.186] (II) CHROME(0): viaPreInit
[ 75.186] (II) CHROME(0): VIAGetRec
[ 75.186] (--) CHROME(0): Chipset: VX900
[ 75.188] (--) CHROME(0): Chipset revision: 0
[ 75.350] (EE) CHROME(0): [drm] Failed to open DRM device for pci:0000:00:01.0: No such file or directory
[ 75.350] (II) Loading sub module "vgahw"
[ 75.350] (II) LoadModule: "vgahw"
[ 75.350] (II) Loading /usr/lib64/xorg/modules/libvgahw.so
[ 75.350] (II) Module vgahw: vendor="X.Org Foundation"
[ 75.350] compiled for 1.18.4, module version = 0.1.0
[ 75.350] ABI class: X.Org Video Driver, version 20.0
[ 75.351] (--) CHROME(0): Probed amount of VideoRAM = 262144 kB
[ 75.351] (II) CHROME(0): Entered viaMapMMIO.
[ 75.351] (--) CHROME(0): Mapping MMIO at address 0xFB000000 with size 52 KB.
[ 75.351] (--) CHROME(0): Mapping 2D Host BitBLT space at address 0xFB200000 with size 2048 KB.
[ 75.351] (--) CHROME(0): Mapping the frame buffer at address 0xD0000000 with size 262144 KB.
[ 75.354] (--) CHROME(0): Frame buffer start address: 0x7f2ba412b000, free start: 0x0 end: 0x10000000
[ 75.354] (II) CHROME(0): Entered viaMMIOEnable.
[ 75.354] (II) CHROME(0): Exiting viaMMIOEnable.
[ 75.354] (II) CHROME(0): vgaHWGetIOBase: hwp->IOBase is 0x03d0
[ 75.354] (II) CHROME(0): Exiting viaMapMMIO.
[ 75.354] (II) CHROME(0): Creating default Display subsection in Screen section
"Default Screen Section" for depth/fbbpp 24/32
[ 75.354] (==) CHROME(0): Depth 24, (--) framebuffer bpp 32
[ 75.354] (==) CHROME(0): RGB weight 888
[ 75.354] (==) CHROME(0): Default visual is TrueColor
[ 75.354] (II) CHROME(0): VIASetupDefaultOptions - Setting up default chipset options.
[ 75.354] (==) CHROME(0): Shadow framebuffer is disabled.
[ 75.354] (==) CHROME(0): Hardware acceleration is enabled.
[ 75.354] (==) CHROME(0): Using EXA acceleration architecture.
[ 75.354] (==) CHROME(0): EXA composite acceleration enabled.
[ 75.354] (==) CHROME(0): EXA scratch area size is 4096 kB.
[ 75.354] (==) CHROME(0): Using hardware two-color cursors and software full-color cursors.
[ 75.354] (==) CHROME(0): GPU virtual command queue will be enabled.
[ 75.354] (==) CHROME(0): DRI IRQ will be enabled if DRI is enabled.
[ 75.354] (==) CHROME(0): AGP DMA will be disabled if DRI is enabled.
[ 75.354] (==) CHROME(0): PCI DMA will not be used for XV image transfer if DRI is enabled.
[ 75.354] (==) CHROME(0): Xv Bandwidth check is enabled.
[ 75.354] (==) CHROME(0): Will not impose a limit on video RAM reserved for DRI.
[ 75.354] (==) CHROME(0): Will try to allocate 32768 kB of AGP memory.
[ 75.354] (==) CHROME(0): TV dotCrawl is disabled.
[ 75.354] (==) CHROME(0): TV deflicker is set to 0.
[ 75.354] (==) CHROME(0): No default TV type is set.
[ 75.354] (==) CHROME(0): No default TV output signal type is set.
[ 75.354] (==) CHROME(0): Will not print VGA registers.
[ 75.354] (==) CHROME(0): Will not scan I2C buses.
[ 75.354] (II) CHROME(0): Detected MemClk 10
[ 75.354] (II) CHROME(0): ViaGetMemoryBandwidth. Memory type: 10
[ 75.354] (II) CHROME(0): Detected TV standard: PAL.
[ 75.355] (II) Loading sub module "ramdac"
[ 75.355] (II) LoadModule: "ramdac"
[ 75.355] (II) Module "ramdac" already built-in
[ 75.355] (II) Loading sub module "i2c"
[ 75.355] (II) LoadModule: "i2c"
[ 75.355] (II) Module "i2c" already built-in
[ 75.355] (II) CHROME(0): Entered ViaI2CInit.
[ 75.355] (II) CHROME(0): Entered ViaI2CBus1Init.
[ 75.355] (II) CHROME(0): I2C bus "I2C Bus 1" initialized.
[ 75.355] (II) CHROME(0): Exiting ViaI2CBus1Init.
[ 75.355] (II) CHROME(0): Entered ViaI2CBus2Init.
[ 75.355] (II) CHROME(0): I2C bus "I2C Bus 2" initialized.
[ 75.355] (II) CHROME(0): Exiting ViaI2CBus2Init.
[ 75.355] (II) CHROME(0): Entered ViaI2CBus3Init.
[ 75.355] (II) CHROME(0): I2C bus "I2C Bus 3" initialized.
[ 75.355] (II) CHROME(0): Exiting ViaI2CBus3Init.
[ 75.355] (II) CHROME(0): Exiting ViaI2CInit.
[ 75.355] (II) Loading sub module "ddc"
[ 75.355] (II) LoadModule: "ddc"
[ 75.355] (II) Module "ddc" already built-in
[ 75.355] (II) CHROME(0): Entered viaOutputDetect.
[ 75.355] (II) CHROME(0): Entered viaProbePinStrapping.
[ 75.355] (II) CHROME(0): Probing VIA Technologies IGP pin strapping . . .
[ 75.355] (II) CHROME(0): SR5A: 0x00
[ 75.355] (II) CHROME(0): Setting 3C5.5A[0] to 0.
[ 75.355] (II) CHROME(0): SR12: 0x00
[ 75.355] (II) CHROME(0): SR13: 0x00
[ 75.355] (II) CHROME(0): Setting 3C5.5A[0] to 1.
[ 75.355] (II) CHROME(0): SR12: 0x00
[ 75.355] (II) CHROME(0): SR13: 0x00
[ 75.355] (II) CHROME(0): LVDS1 + LVDS2 detected.
[ 75.355] (II) CHROME(0): Exiting viaProbePinStrapping.
[ 75.355] (II) CHROME(0): Entered via_analog_init.
[ 75.355] (II) CHROME(0): Output VGA-1 has no monitor section
[ 75.355] (II) CHROME(0): Exiting via_analog_init.
[ 75.355] (II) CHROME(0): Entered via_tv_init.
[ 75.357] (--) CHROME(0): Did not detect a TV encoder.
[ 75.357] (II) CHROME(0): Exiting via_tv_init.
[ 75.357] (II) CHROME(0): Entered via_dvi_init.
[ 75.357] (II) CHROME(0): Entered viaTMDSInit.
[ 75.357] (II) CHROME(0): SR13: 0x00
[ 75.357] (II) CHROME(0): Integrated TMDS transmitter not found.
[ 75.357] (II) CHROME(0): Exiting viaTMDSInit.
[ 75.357] (II) CHROME(0): Integrated TMDS transmitter for DVI not found.
[ 75.357] (II) CHROME(0): Probing I2C Bus 2 for VT1632.
[ 75.357] (II) CHROME(0): Entered viaVT1632Init.
[ 75.357] (--) CHROME(0): I2C device not found.
[ 75.357] (II) CHROME(0): Exiting viaVT1632Init.
[ 75.357] (II) CHROME(0): I2C Bus 2 was not initialized for DVI use.
[ 75.358] (II) CHROME(0): Probing I2C Bus 3 for VT1632.
[ 75.358] (II) CHROME(0): Entered viaVT1632Init.
[ 75.358] (--) CHROME(0): I2C device not found.
[ 75.358] (II) CHROME(0): Exiting viaVT1632Init.
[ 75.358] (II) CHROME(0): I2C Bus 3 was not initialized for DVI use.
[ 75.358] (II) CHROME(0): Probing I2C Bus 2 for SiI 164.
[ 75.358] (II) CHROME(0): Entered viaSiI164Init.
[ 75.359] (--) CHROME(0): I2C device not found.
[ 75.359] (II) CHROME(0): Exiting viaSiI164Init.
[ 75.359] (II) CHROME(0): I2C Bus 2 was not initialized for DVI use.
[ 75.359] (II) CHROME(0): Probing I2C Bus 3 for SiI 164.
[ 75.359] (II) CHROME(0): Entered viaSiI164Init.
[ 75.359] (--) CHROME(0): I2C device not found.
[ 75.359] (II) CHROME(0): Exiting viaSiI164Init.
[ 75.359] (II) CHROME(0): I2C Bus 3 was not initialized for DVI use.
[ 75.359] (II) CHROME(0): Exiting via_dvi_init.
[ 75.359] (==) CHROME(0): LVDS-0 : DVI Center is disabled.
[ 75.359] (II) CHROME(0): Output FP-1 has no monitor section
[ 75.359] (II) CHROME(0): Exiting viaOutputDetect.
[ 75.359] (--) CHROME(0): Probing for a VGA monitor on I2C Bus 1.
[ 75.359] (II) CHROME(0): I2C device "I2C Bus 1:ddc2" registered at address 0xA0.
[ 75.366] (--) CHROME(0): Did not detect a VGA monitor on I2C Bus 1.
[ 75.366] (--) CHROME(0): Probing for a VGA monitor on I2C Bus 2.
[ 75.366] (II) CHROME(0): I2C device "I2C Bus 2:ddc2" registered at address 0xA0.
[ 75.370] (--) CHROME(0): Did not detect a VGA monitor on I2C Bus 2.
[ 75.370] (--) CHROME(0): Now perform manual detection of a VGA monitor.
[ 75.370] (II) CHROME(0): EDID for output VGA-1
[ 75.370] (II) CHROME(0): Entered via_lvds_detect.
[ 75.370] (II) CHROME(0): Entered viaLVDSGetFPInfoFromScratchPad.
[ 75.370] (II) CHROME(0): VIA Technologies VGA BIOS Scratch Pad Register Flat Panel Index: 10
[ 75.370] (II) CHROME(0): Flat Panel Native Resolution: 1368x768
[ 75.370] (II) CHROME(0): Flat Panel Dual Edge Transfer: Off
[ 75.370] (II) CHROME(0): Flat Panel Output Color Dithering: Off (24 bit)
[ 75.370] (II) CHROME(0): Exiting viaLVDSGetFPInfoFromScratchPad.
[ 75.370] (II) CHROME(0): Exiting via_lvds_detect.
[ 75.370] (II) CHROME(0): Entered via_lvds_get_modes.
[ 75.370] (II) CHROME(0): Exiting via_lvds_get_modes.
[ 75.371] (II) CHROME(0): Printing probed modes for output FP-1
[ 75.371] (II) CHROME(0): Modeline "1368x768"x59.9 85.25 1368 1440 1576 1784 768 771 781 798 -hsync +vsync (47.8 kHz eP)
[ 75.371] (II) CHROME(0): Output VGA-1 disconnected
[ 75.371] (II) CHROME(0): Output FP-1 connected
[ 75.371] (II) CHROME(0): Using exact sizes for initial modes
[ 75.371] (II) CHROME(0): Output FP-1 using initial mode 1368x768 +0+0
[ 75.371] (II) CHROME(0): Using default gamma of (1.0, 1.0, 1.0) unless otherwise stated.
[ 75.371] (==) CHROME(0): DPI set to (96, 96)
[ 75.371] (II) Loading sub module "fb"
[ 75.371] (II) LoadModule: "fb"
[ 75.371] (II) Loading /usr/lib64/xorg/modules/libfb.so
[ 75.372] (II) Module fb: vendor="X.Org Foundation"
[ 75.372] compiled for 1.18.4, module version = 1.0.0
[ 75.372] ABI class: X.Org ANSI C Emulation, version 0.4
[ 75.372] (II) Loading sub module "exa"
[ 75.372] (II) LoadModule: "exa"
[ 75.372] (II) Loading /usr/lib64/xorg/modules/libexa.so
[ 75.372] (II) Module exa: vendor="X.Org Foundation"
[ 75.373] compiled for 1.18.4, module version = 2.6.0
[ 75.373] ABI class: X.Org Video Driver, version 20.0
[ 75.373] (--) Depth 24 pixmap format is 32 bpp
[ 75.373] (II) CHROME(0): VIAScreenInit
[ 75.373] (II) CHROME(0): Frame Buffer From (0,0) To (1368,32767)
[ 75.373] (II) CHROME(0): Using 31999 lines for offscreen memory.
[ 75.373] 4202496 bytes of Linear memory allocated at ab00000, handle 27281632
[ 75.373] (II) CHROME(0): Entered umsAccelInit.
[ 75.373] 262144 bytes of Linear memory allocated at af02000, handle 27281776
[ 75.373] (II) CHROME(0): Initializing the 2D engine.
[ 75.373] (II) CHROME(0): Initializing the 3D engine.
[ 75.373] 32 bytes of Linear memory allocated at af42000, handle 27281920
[ 75.373] 32 bytes of Linear memory allocated at af42080, handle 27282208
[ 75.373] (II) CHROME(0): Exiting umsAccelInit.
[ 75.373] (II) CHROME(0): - Visuals set up
[ 75.373] (II) CHROME(0): - B & W
[ 75.373] (**) CHROME(0): Option "MigrationHeuristic" "greedy"
[ 75.373] (II) EXA(0): Offscreen pixmap area of 264232960 bytes
[ 75.373] (II) EXA(0): Driver registered support for the following operations:
[ 75.373] (II) Solid
[ 75.373] (II) Copy
[ 75.373] (II) Composite (RENDER acceleration)
[ 75.373] (II) CHROME(0): [EXA] Enabled EXA acceleration.
[ 75.373] (==) CHROME(0): Backing store enabled
[ 75.373] (II) CHROME(0): - Backing store set up
[ 75.374] (II) CHROME(0): - SW cursor set up
[ 75.374] (II) CHROME(0): HWCursor ARGB enabled
[ 75.374] 16384 bytes of Linear memory allocated at af42100, handle 27305392
[ 75.374] 16384 bytes of Linear memory allocated at af46100, handle 27305472
[ 75.374] (II) CHROME(0): RandR 1.2 enabled, ignore the following RandR disabled message.
[ 75.374] (II) CHROME(0): - Def Color map set up
[ 75.374] (II) CHROME(0): - Palette loaded
[ 75.374] (II) CHROME(0): - Color maps etc. set up
[ 75.374] (==) CHROME(0): DPMS enabled
[ 75.374] (II) CHROME(0): - DPMS set up
[ 75.374] (II) CHROME(0): VIAEnterVT
[ 75.374] (II) CHROME(0): Entered viaIGA1Save.
[ 75.375] (II) CHROME(0): Saving sequencer registers.
[ 75.375] (II) CHROME(0): Finished saving sequencer registers.
[ 75.375] (II) CHROME(0): Saving IGA1 registers.
[ 75.375] (II) CHROME(0): Finished saving IGA1 registers.
[ 75.375] (II) CHROME(0): Exiting viaIGA1Save.
[ 75.375] (II) CHROME(0): Entered iga2_crtc_save.
[ 75.375] (II) CHROME(0): Entered viaIGA2Save.
[ 75.375] (II) CHROME(0): Saving IGA2 registers.
[ 75.375] (II) CHROME(0): Finished saving IGA2 registers.
[ 75.375] (II) CHROME(0): Exiting viaIGA2Save.
[ 75.375] (II) CHROME(0): Exiting iga2_crtc_save.
[ 75.375] (II) CHROME(0): Entered via_analog_dpms.
[ 75.375] (II) CHROME(0): Entered viaAnalogOutput.
[ 75.375] (II) CHROME(0): Analog VGA Output: Off
[ 75.375] (II) CHROME(0): Exiting viaAnalogOutput.
[ 75.375] (II) CHROME(0): Exiting via_analog_dpms.
[ 75.375] (II) CHROME(0): Entered ViaLVDSPower.
[ 75.375] (II) CHROME(0): Integrated LVDS Flat Panel Power: Off
[ 75.375] (II) CHROME(0): Exiting ViaLVDSPower.
[ 75.375] (II) CHROME(0): Entered viaFPIOPadSetting.
[ 75.375] (II) CHROME(0): SR5A: 0x00
[ 75.375] (II) CHROME(0): Setting 3C5.5A[0] to 0.
[ 75.375] (II) CHROME(0): SR12: 0x00
[ 75.375] (II) CHROME(0): SR13: 0x00
[ 75.375] (II) CHROME(0): Entered viaLVDS1SetIOPadSetting.
[ 75.375] (II) CHROME(0): LVDS1 I/O Pad State: 0
[ 75.375] (II) CHROME(0): Exiting viaLVDS1SetIOPadSetting.
[ 75.375] (II) CHROME(0): Entered viaLVDS2SetIOPadSetting.
[ 75.375] (II) CHROME(0): LVDS2 I/O Pad State: 0
[ 75.375] (II) CHROME(0): Exiting viaLVDS2SetIOPadSetting.
[ 75.375] (II) CHROME(0): Restoring 3C5.5A[0].
[ 75.375] (II) CHROME(0): Exiting viaFPIOPadSetting.
[ 75.376] (II) CHROME(0): Entered iga1_crtc_dpms.
[ 75.376] (II) CHROME(0): Entered viaIGA1DPMSControl.
[ 75.376] (II) CHROME(0): Exiting viaIGA1DPMSControl.
[ 75.376] (II) CHROME(0): Exiting iga1_crtc_dpms.
[ 75.376] (II) CHROME(0): Entered iga2_crtc_dpms.
[ 75.376] (II) CHROME(0): Entered viaIGA2DisplayOutput.
[ 75.376] (II) CHROME(0): IGA2 Display Output: Off
[ 75.376] (II) CHROME(0): Exiting viaIGA2DisplayOutput.
[ 75.376] (II) CHROME(0): Exiting iga2_crtc_dpms.
[ 75.376] (II) CHROME(0): Entered viaIGA2ModeValid.
[ 75.376] (II) CHROME(0): Exiting viaIGA2ModeValid.
[ 75.376] (II) CHROME(0): Entered ViaLVDSPower.
[ 75.376] (II) CHROME(0): Integrated LVDS Flat Panel Power: Off
[ 75.376] (II) CHROME(0): Exiting ViaLVDSPower.
[ 75.376] (II) CHROME(0): Entered viaFPIOPadSetting.
[ 75.376] (II) CHROME(0): SR5A: 0x00
[ 75.376] (II) CHROME(0): Setting 3C5.5A[0] to 0.
[ 75.376] (II) CHROME(0): SR12: 0x00
[ 75.376] (II) CHROME(0): SR13: 0x00
[ 75.376] (II) CHROME(0): Entered viaLVDS1SetIOPadSetting.
[ 75.376] (II) CHROME(0): LVDS1 I/O Pad State: 0
[ 75.376] (II) CHROME(0): Exiting viaLVDS1SetIOPadSetting.
[ 75.376] (II) CHROME(0): Entered viaLVDS2SetIOPadSetting.
[ 75.376] (II) CHROME(0): LVDS2 I/O Pad State: 0
[ 75.376] (II) CHROME(0): Exiting viaLVDS2SetIOPadSetting.
[ 75.376] (II) CHROME(0): Restoring 3C5.5A[0].
[ 75.376] (II) CHROME(0): Exiting viaFPIOPadSetting.
[ 75.376] (II) CHROME(0): Entered viaFPIOPadSetting.
[ 75.376] (II) CHROME(0): SR5A: 0x00
[ 75.376] (II) CHROME(0): Setting 3C5.5A[0] to 0.
[ 75.376] (II) CHROME(0): SR12: 0x00
[ 75.376] (II) CHROME(0): SR13: 0x00
[ 75.376] (II) CHROME(0): Entered viaLVDS1SetIOPadSetting.
[ 75.376] (II) CHROME(0): LVDS1 I/O Pad State: 0
[ 75.376] (II) CHROME(0): Exiting viaLVDS1SetIOPadSetting.
[ 75.376] (II) CHROME(0): Entered viaLVDS2SetIOPadSetting.
[ 75.376] (II) CHROME(0): LVDS2 I/O Pad State: 0
[ 75.376] (II) CHROME(0): Exiting viaLVDS2SetIOPadSetting.
[ 75.376] (II) CHROME(0): Restoring 3C5.5A[0].
[ 75.376] (II) CHROME(0): Exiting viaFPIOPadSetting.
[ 75.376] (II) CHROME(0): Entered iga2_crtc_prepare.
[ 75.376] (II) CHROME(0): Entered viaIGA2DisplayOutput.
[ 75.376] (II) CHROME(0): IGA2 Display Output: Off
[ 75.376] (II) CHROME(0): Exiting viaIGA2DisplayOutput.
[ 75.377] (II) CHROME(0): Exiting iga2_crtc_prepare.
[ 75.377] (II) CHROME(0): Entered iga2_crtc_mode_set.
[ 75.377] (II) CHROME(0): Entered viaIGA2HWReset.
[ 75.377] (II) CHROME(0): IGA2 HW Reset: On
[ 75.377] (II) CHROME(0): Exiting viaIGA2HWReset.
[ 75.377] (II) CHROME(0): Entered viaIGA2DisplayChannel.
[ 75.377] (II) CHROME(0): IGA2 Display Channel: Off
[ 75.377] (II) CHROME(0): Exiting viaIGA2DisplayChannel.
[ 75.377] (II) CHROME(0): Entered viaIGAInitCommon.
[ 75.377] (II) CHROME(0): Enable Register: 0x01
[ 75.377] (II) CHROME(0): Misc. Register: 0x6F
[ 75.377] (II) CHROME(0): Enable Register: 0x01
[ 75.377] (II) CHROME(0): Misc. Register: 0x6F
[ 75.377] (II) CHROME(0): SR15: 0x22
[ 75.377] (II) CHROME(0): SR19: 0x7F
[ 75.377] (II) CHROME(0): SR1A: 0x88
[ 75.377] (II) CHROME(0): SR1E: 0x01
[ 75.377] (II) CHROME(0): SR2D: 0x3F
[ 75.377] (II) CHROME(0): SR2E: 0xFB
[ 75.377] (II) CHROME(0): SR3F: 0xFF
[ 75.377] (II) CHROME(0): CR36: 0x31
[ 75.377] (II) CHROME(0): CR3B: 0x03
[ 75.377] (II) CHROME(0): CR3C: 0x08
[ 75.377] (II) CHROME(0): CR3D: 0xA4
[ 75.377] (II) CHROME(0): CR3E: 0x00
[ 75.377] (II) CHROME(0): CR3F: 0x0A
[ 75.377] (II) CHROME(0): CR47: 0x04
[ 75.377] (II) CHROME(0): CR6B: 0x04
[ 75.377] (II) CHROME(0): Exiting viaIGAInitCommon.
[ 75.377] (II) CHROME(0): Entered viaIGA2Init.
[ 75.377] (II) CHROME(0): SR1B: 0xF0
[ 75.377] (II) CHROME(0): SR2D: 0x3F
[ 75.377] (II) CHROME(0): CR6A: 0x00
[ 75.377] (II) CHROME(0): CR6B: 0x04
[ 75.377] (II) CHROME(0): CR6C: 0x00
[ 75.377] (II) CHROME(0): CR79: 0x9E
[ 75.377] (II) CHROME(0): Exiting viaIGA2Init.
[ 75.377] (II) CHROME(0): Modeline "1368x768"x59.9 85.25 1368 1440 1576 1784 768 771 781 798 -hsync +vsync (47.8 kHz eP)
[ 75.377] (II) CHROME(0): CrtcHDisplay: 0x558
[ 75.377] (II) CHROME(0): CrtcHBlankStart: 0x558
[ 75.377] (II) CHROME(0): CrtcHSyncStart: 0x5a0
[ 75.377] (II) CHROME(0): CrtcHSyncEnd: 0x628
[ 75.377] (II) CHROME(0): CrtcHBlankEnd: 0x6f8
[ 75.377] (II) CHROME(0): CrtcHTotal: 0x6f8
[ 75.377] (II) CHROME(0): CrtcHSkew: 0x0
[ 75.377] (II) CHROME(0): CrtcVDisplay: 0x300
[ 75.377] (II) CHROME(0): CrtcVBlankStart: 0x300
[ 75.377] (II) CHROME(0): CrtcVSyncStart: 0x303
[ 75.377] (II) CHROME(0): CrtcVSyncEnd: 0x30d
[ 75.377] (II) CHROME(0): CrtcVBlankEnd: 0x31e
[ 75.377] (II) CHROME(0): CrtcVTotal: 0x31e
[ 75.377] (II) CHROME(0): Entered viaIGA2SetColorDepth.
[ 75.377] (II) CHROME(0): IGA2 Color Depth: 32 bit
[ 75.377] (II) CHROME(0): Exiting viaIGA2SetColorDepth.
[ 75.377] (II) CHROME(0): Entered viaIGA2SetDisplayRegister.
[ 75.377] (II) CHROME(0): Requested Screen Mode: 1368x768
[ 75.377] (II) CHROME(0): IGA2 CrtcHTotal: 1784
[ 75.377] (II) CHROME(0): IGA2 CrtcHDisplay: 1368
[ 75.377] (II) CHROME(0): IGA2 CrtcHBlankStart: 1368
[ 75.377] (II) CHROME(0): IGA2 CrtcHBlankEnd: 1784
[ 75.377] (II) CHROME(0): IGA2 CrtcHSyncStart: 1440
[ 75.377] (II) CHROME(0): IGA2 CrtcHSyncEnd: 1576
[ 75.378] (II) CHROME(0): IGA2 CrtcVTotal: 798
[ 75.378] (II) CHROME(0): IGA2 CrtcVDisplay: 768
[ 75.378] (II) CHROME(0): IGA2 CrtcVBlankStart: 768
[ 75.378] (II) CHROME(0): IGA2 CrtcVBlankEnd: 798
[ 75.378] (II) CHROME(0): IGA2 CrtcVSyncStart: 771
[ 75.378] (II) CHROME(0): IGA2 CrtcVSyncEnd: 781
[ 75.378] (II) CHROME(0): Exiting viaIGA2SetDisplayRegister.
[ 75.378] (II) CHROME(0): ViaSetSecondaryFIFO
[ 75.378] (II) CHROME(0): ViaSetDotclock to 0x0770a9
[ 75.378] (II) CHROME(0): ViaSetUseExternalClock
[ 75.378] (II) CHROME(0): Entered viaIGA2SetFBStartingAddress.
[ 75.378] (II) CHROME(0): Base Address: 0x0
[ 75.378] (II) CHROME(0): DRI Base Address: 0x1560000
[ 75.378] (II) CHROME(0): CR62: 0x00
[ 75.378] (II) CHROME(0): CR63: 0x00
[ 75.378] (II) CHROME(0): CR64: 0xAC
[ 75.378] (II) CHROME(0): CRA3: 0x02
[ 75.378] (II) CHROME(0): Exiting viaIGA2SetFBStartingAddress.
[ 75.378] (II) CHROME(0): Entered viaIGA2DisplayChannel.
[ 75.378] (II) CHROME(0): IGA2 Display Channel: On
[ 75.378] (II) CHROME(0): Exiting viaIGA2DisplayChannel.
[ 75.378] (II) CHROME(0): Entered viaIGA2HWReset.
[ 75.378] (II) CHROME(0): IGA2 HW Reset: Off
[ 75.378] (II) CHROME(0): Exiting viaIGA2HWReset.
[ 75.378] (II) CHROME(0): Exiting iga2_crtc_mode_set.
[ 75.378] (II) CHROME(0): Entered viaLVDS1SetDisplaySource.
[ 75.378] (II) CHROME(0): LVDS1 Integrated LVDS Transmitter Display Output Source: IGA2
[ 75.378] (II) CHROME(0): Exiting viaLVDS1SetDisplaySource.
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