dri-devel January 2021

dri-devel@lists.freedesktop.org

322 participants
737 discussions

[PATCH 1/3] drm/msm: Fix race of GPU init vs timestamp power management.
by Eric Anholt 29 Jan '21

29 Jan '21

We were using the same force-poweron bit in the two codepaths, so they could race to have one of them lose GPU power early. Signed-off-by: Eric Anholt <eric(a)anholt.net> Cc: stable(a)vger.kernel.org # v5.9 --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 25 ++++++++++++++++++++++--- drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 8 ++++++++ drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 4 ++-- 3 files changed, 32 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index 78836b4fb98e..378dc7f190c3 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -264,6 +264,16 @@ int _a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state, char } name = "GPU_SET"; break; + case GMU_OOB_PERFCOUNTER_SET: + if (gmu->legacy) { + request = GMU_OOB_PERFCOUNTER_REQUEST; + ack = GMU_OOB_PERFCOUNTER_ACK; + } else { + request = GMU_OOB_PERFCOUNTER_REQUEST_NEW; + ack = GMU_OOB_PERFCOUNTER_ACK_NEW; + } + name = "PERFCOUNTER"; + break; case GMU_OOB_BOOT_SLUMBER: request = GMU_OOB_BOOT_SLUMBER_REQUEST; ack = GMU_OOB_BOOT_SLUMBER_ACK; @@ -302,9 +312,14 @@ int _a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state, char void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state) { if (!gmu->legacy) { - WARN_ON(state != GMU_OOB_GPU_SET); - gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, - 1 << GMU_OOB_GPU_SET_CLEAR_NEW); + if (state == GMU_OOB_GPU_SET) { + gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, + 1 << GMU_OOB_GPU_SET_CLEAR_NEW); + } else { + WARN_ON(state != GMU_OOB_PERFCOUNTER_SET); + gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, + 1 << GMU_OOB_PERFCOUNTER_CLEAR_NEW); + } return; } @@ -313,6 +328,10 @@ void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state) gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << GMU_OOB_GPU_SET_CLEAR); break; + case GMU_OOB_PERFCOUNTER_SET: + gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, + 1 << GMU_OOB_PERFCOUNTER_CLEAR); + break; case GMU_OOB_BOOT_SLUMBER: gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << GMU_OOB_BOOT_SLUMBER_CLEAR); diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h index c6d2bced8e5d..9fa278de2106 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h @@ -156,6 +156,7 @@ enum a6xx_gmu_oob_state { GMU_OOB_BOOT_SLUMBER = 0, GMU_OOB_GPU_SET, GMU_OOB_DCVS_SET, + GMU_OOB_PERFCOUNTER_SET, }; /* These are the interrupt / ack bits for each OOB request that are set @@ -190,6 +191,13 @@ enum a6xx_gmu_oob_state { #define GMU_OOB_GPU_SET_ACK_NEW 31 #define GMU_OOB_GPU_SET_CLEAR_NEW 31 +#define GMU_OOB_PERFCOUNTER_REQUEST 17 +#define GMU_OOB_PERFCOUNTER_ACK 25 +#define GMU_OOB_PERFCOUNTER_CLEAR 25 + +#define GMU_OOB_PERFCOUNTER_REQUEST_NEW 28 +#define GMU_OOB_PERFCOUNTER_ACK_NEW 30 +#define GMU_OOB_PERFCOUNTER_CLEAR_NEW 30 void a6xx_hfi_init(struct a6xx_gmu *gmu); int a6xx_hfi_start(struct a6xx_gmu *gmu, int boot_state); diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index c8a9010c1a1d..7424a70b9d35 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1177,12 +1177,12 @@ static int a6xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value) struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); /* Force the GPU power on so we can read this register */ - a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); + a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET); *value = gpu_read64(gpu, REG_A6XX_RBBM_PERFCTR_CP_0_LO, REG_A6XX_RBBM_PERFCTR_CP_0_HI); - a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); + a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET); return 0; } -- 2.30.0

3 9

[PULL] drm-intel-next
by Rodrigo Vivi 29 Jan '21

29 Jan '21

Hi Dave and Daniel, On my last pull request I incorrectly stated that Async flips were enabled for all ilk+ platforms, while it was only on SKL. I'm sorry about that. I hope there's still time to include a few changes including the actual patches that make this statement true for 5.12. Along with other fixes and clean-up as described below: Here goes drm-intel-next-2021-01-29: - WARN if plane src coords are too big (Ville) - Prevent double YUV range correction on HDR planes (Andres) - DP MST related Fixes (Sean, Imre) - More clean-up around DRAM detection code (Jose) - Actually async flips enable for all ilk+ platforms (Ville) Sorry and Thanks, Rodrigo. The following changes since commit 784953a46589276b38d7e6dcb5ebf7e29db72ff1: drm/i915/display/vrr: Skip the VRR HW state readout on DSI transcoder (2021-01-26 16:34:53 -0800) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-next-2021-01-29 for you to fetch changes up to 3b7bbb3619d2cc92f04ba10ad27d3b616aabf175: drm/i915/dp: Prevent setting the LTTPR LT mode if no LTTPRs are detected (2021-01-29 22:00:07 +0200) ---------------------------------------------------------------- - WARN if plane src coords are too big (Ville) - Prevent double YUV range correction on HDR planes (Andres) - DP MST related Fixes (Sean, Imre) - More clean-up around DRAM detection code (Jose) - Actually async flips enable for all ilk+ platforms (Ville) ---------------------------------------------------------------- Andres Calderon Jaramillo (1): drm/i915/display: Prevent double YUV range correction on HDR planes Imre Deak (3): drm/dp/mst: Export drm_dp_get_vc_payload_bw() drm/i915: Fix the MST PBN divider calculation drm/i915/dp: Prevent setting the LTTPR LT mode if no LTTPRs are detected José Roberto de Souza (3): drm/i915: Nuke not needed members of dram_info drm/i915/gen11+: Only load DRAM information from pcode drm/i915: Rename is_16gb_dimm to wm_lv_0_adjust_needed Sean Paul (1): drm/i915/hdcp: Disable the QSES check for HDCP 1.4 over MST Ville Syrjälä (6): drm/i915: WARN if plane src coords are too big drm/i915: Limit plane stride to below TILEOFF.x limit drm/i915: Implement async flips for bdw drm/i915: Implement async flip for ivb/hsw drm/i915: Implement async flip for ilk/snb drm/i915: Implement async flips for vlv/chv drivers/gpu/drm/drm_dp_mst_topology.c | 24 ++- drivers/gpu/drm/i915/display/i9xx_plane.c | 213 ++++++++++++++++++++- drivers/gpu/drm/i915/display/i9xx_plane.h | 2 +- drivers/gpu/drm/i915/display/intel_bw.c | 80 +------- drivers/gpu/drm/i915/display/intel_display.c | 16 +- drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 12 +- .../gpu/drm/i915/display/intel_dp_link_training.c | 36 ++-- drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 +- drivers/gpu/drm/i915/display/intel_sprite.c | 98 ++++------ drivers/gpu/drm/i915/i915_drv.c | 9 +- drivers/gpu/drm/i915/i915_drv.h | 6 +- drivers/gpu/drm/i915/i915_irq.c | 39 ++-- drivers/gpu/drm/i915/i915_reg.h | 3 + drivers/gpu/drm/i915/intel_dram.c | 136 +++++++++---- drivers/gpu/drm/i915/intel_pm.c | 2 +- include/drm/drm_dp_mst_helper.h | 1 + 16 files changed, 434 insertions(+), 247 deletions(-)

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[pull] amdgpu, amdkfd drm-next-5.12
by Alex Deucher 29 Jan '21

29 Jan '21

Hi Dave, Daniel, Fixes for 5.12. The following changes since commit a6b8720c2f85143561c3453e1cf928a2f8586ac0: Merge tag 'amd-drm-next-5.12-2021-01-20' of https://gitlab.freedesktop.org/agd5f/linux into drm-next (2021-01-20 13:08:18 +0100) are available in the Git repository at: https://gitlab.freedesktop.org/agd5f/linux.git tags/amd-drm-next-5.12-2021-01-29 for you to fetch changes up to efa18405baa55a864c61d2f3cc6fe4d363818eb3: drm/amd/display: Fix HDMI deep color output for DCE 6-11. (2021-01-25 17:49:47 -0500) ---------------------------------------------------------------- amd-drm-next-5.12-2021-01-29: amdgpu: - Display fixes and cleanups - Vangogh fixes - Fix possible race when there are timeouts on two rings - SR-IOV fixes - Add missing license - DCE 10/12 bpc fixes - Display MALL fixes - Fix SMU user preference settings persistence amdkfd: - Fix config handling ---------------------------------------------------------------- Aaron Liu (1): drm/amdgpu: update mmhub mgcg&ls for mmhub_v2_3 Anthony Koo (1): drm/amd/display: [FW Promotion] Release 0.0.48 Aric Cyr (2): drm/amd/display: Allow PSTATE chnage when no displays are enabled drm/amd/display: 3.2.119 Arnd Bergmann (1): amdgpu: fix clang build warning Arunpravin (1): drm/amd/pm: store and reinstate swsmu user power configurations Bhawanpreet Lakha (3): drm/amd/display: Enable programing of MALL watermarks drm/amd/display: Dynamic cursor cache size for MALL eligibility check drm/amd/display: Update dcn30_apply_idle_power_optimizations() code Bing Guo (2): drm/amd/display: Change function decide_dp_link_settings to avoid infinite looping drm/amd/display: Fix dml20v2_ModeSupportAndSystemConfigurationFull() to check DesiredBPP. Colin Ian King (2): drm/amd/display: Fix spelling mistake of function name drm/amdgpu: Fix masking binary not operator on two mask operations Dan Carpenter (1): drm/amd/display: Fix a potential NULL dereference Feifei Xu (1): drm/amdgpu:Add pcie gen5 support in pcie capability. Felix Kuehling (2): drm/amdkfd: Enable userptr support when KFD is enabled drm/amdgpu: Make contiguous pinning optional George Shen (1): drm/amd/display: Log link/connector info provided in BIOS object table Horace Chen (1): drm/amdgpu: race issue when jobs on 2 ring timeout Huang Rui (2): drm/amd/pm: print the timeout of smc message drm/amdgpu: remove gpu info firmware of green sardine Jake Wang (1): drm/amd/display: Update dram_clock_change_latency for DCN2.1 Jiapeng Zhong (1): drm/amdgpu: Assign boolean values to a bool variable Jingwen Chen (2): drm/amd/amdgpu: remove redundant flush_delayed_work drm/amd/amdgpu: add error handling to amdgpu_virt_read_pf2vf_data Jinzhou Su (4): drm/amdgpu: Remove GFXOFF MASK for Vangogh drm/amdgpu: modify GCR_GENERAL_CNTL for Vangogh drm/amdgpu: Add RLC_PG_DELAY_3 for Vangogh drm/amdgpu: Allow GfxOff on Vangogh as default Jonathan Gray (1): drm/amd/display: change license of color_table.c Kevin Wang (1): drm/amd/pm: remove unused message SMU_MSG_SpareX Lang Yu (1): drm/amd/display: fix 64-bit division issue on 32-bit OS Mario Kleiner (2): drm/amd/display: Fix 10/12 bpc setup in DCE output bit depth reduction. drm/amd/display: Fix HDMI deep color output for DCE 6-11. Mike Hsieh (1): drm/amd/display: disable FEC while using eDP Nicholas Kazlauskas (4): drm/amd/display: Use hardware sequencer functions for PG control drm/amd/display: Allow dmub srv hardware reset before HW init drm/amd/display: Guard against NULL pointer deref when get_i2c_info fails drm/amd/display: Fix reset sequence with driver direct DMCUB fw load Pratik Vishwakarma (1): Revert "drm/amd/display: Tune min clk values for MPO for RV" Prike Liang (1): drm/amdgpu/pm: no need GPU status set since mmnbif_gpu_BIF_DOORBELL_FENCE_CNTL added in FSDL Stylon Wang (1): drm/amd/display: Report Freesync to vrr_range debugfs entry in DRM Sung Lee (1): drm/amd/display: DCN2X Find Secondary Pipe properly in MPO + ODM Case Vladimir Stempen (1): drm/amd/display: Fixed corruptions on HPDRX link loss restore Wyatt Wood (1): drm/amd/display: Allow dmu_stg to support cached inbox for dmub drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 86 ++++++++-- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 7 +- drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 7 +- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 23 ++- drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c | 84 +++++++--- drivers/gpu/drm/amd/amdkfd/Kconfig | 2 + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 + .../gpu/drm/amd/display/dc/bios/command_table.c | 61 +++++++ .../drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c | 30 +--- .../amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c | 24 +-- drivers/gpu/drm/amd/display/dc/core/dc.c | 12 +- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 28 +++- drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c | 6 + drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 7 +- drivers/gpu/drm/amd/display/dc/dc.h | 8 +- .../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 14 ++ .../drm/amd/display/dc/dce/dce_stream_encoder.c | 1 + drivers/gpu/drm/amd/display/dc/dce/dce_transform.c | 8 +- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 18 +- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 9 +- .../gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 7 +- .../gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 2 +- drivers/gpu/drm/amd/display/dc/dcn30/Makefile | 6 +- drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 182 ++++++++++++++++----- drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h | 3 +- drivers/gpu/drm/amd/display/dc/dcn301/Makefile | 3 +- drivers/gpu/drm/amd/display/dc/dcn302/Makefile | 3 +- .../drm/amd/display/dc/dcn302/dcn302_resource.c | 5 +- .../display/dc/dml/dcn20/display_mode_vba_20v2.c | 117 ++++++++----- .../display/dc/dml/dcn30/display_rq_dlg_calc_30.c | 32 ++-- drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 3 +- drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 9 +- drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c | 11 +- drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c | 9 +- .../drm/amd/display/modules/color/color_table.c | 26 ++- drivers/gpu/drm/amd/include/amd_pcie.h | 2 + drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 15 ++ drivers/gpu/drm/amd/pm/inc/smu_types.h | 2 - drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 148 ++++++++++++++++- drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 2 - drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 4 +- drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 11 +- 42 files changed, 806 insertions(+), 235 deletions(-)

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[git pull] drm fixes for 5.11-rc6
by Dave Airlie 29 Jan '21

29 Jan '21

Hey Linus, Weekly fixes for graphics, nothing too major, nouveau has a few regression fixes for various fallout from header changes previously, vc4 has two fixes, two amdgpu, and a smattering of i915 fixes. All seems on course for a quieter rc7, fingers crossed. Dave. drm-fixes-2021-01-29: drm fixes for 5.11-rc6 nouveau: - fix svm init conditions - fix nv50 modesetting regression - fix cursor plane modifiers - fix > 64x64 cursor regression vc4: - Fix LBM size calculation - Fix high resolutions for hvs5 i915: - Fix ICL MG PHY vswing - Fix subplatform handling - Fix selftest memleak - Clear CACHE_MODE prior to clearing residuals - Always flush the active worker before returning from the wait - Always try to reserve GGTT address 0x0 amdgpu: - Fix a fan control regression on some boards - Fix clang warning The following changes since commit 6ee1d745b7c9fd573fba142a2efdad76a9f1cb04: Linux 5.11-rc5 (2021-01-24 16:47:14 -0800) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm tags/drm-fixes-2021-01-29 for you to fetch changes up to e0ecafede87eb1a3d1e708f0365fad0d59489285: Merge tag 'amd-drm-fixes-5.11-2021-01-28' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixes (2021-01-29 11:36:38 +1000) ---------------------------------------------------------------- drm fixes for 5.11-rc6 nouveau: - fix svm init conditions - fix nv50 modesetting regression - fix cursor plane modifiers - fix > 64x64 cursor regression vc4: - Fix LBM size calculation - Fix high resolutions for hvs5 i915: - Fix ICL MG PHY vswing - Fix subplatform handling - Fix selftest memleak - Clear CACHE_MODE prior to clearing residuals - Always flush the active worker before returning from the wait - Always try to reserve GGTT address 0x0 amdgpu: - Fix a fan control regression on some boards - Fix clang warning ---------------------------------------------------------------- Alex Deucher (1): Revert "drm/amdgpu/swsmu: drop set_fan_speed_percent (v2)" Arnd Bergmann (1): amdgpu: fix clang build warning Bastian Beranek (1): drm/nouveau/dispnv50: Restore pushing of all data. Ben Skeggs (1): drm/nouveau/nvif: fix method count when pushing an array Chris Wilson (3): drm/i915/gt: Clear CACHE_MODE prior to clearing residuals drm/i915: Always flush the active worker before returning from the wait drm/i915/gt: Always try to reserve GGTT address 0x0 Dave Airlie (4): Merge branch '04.01-ampere-lite' of git://github.com/skeggsb/linux into drm-fixes Merge tag 'drm-misc-fixes-2021-01-27' of git://anongit.freedesktop.org/drm/drm-misc into drm-fixes Merge tag 'drm-intel-fixes-2021-01-28' of git://anongit.freedesktop.org/drm/drm-intel into drm-fixes Merge tag 'amd-drm-fixes-5.11-2021-01-28' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixes Dom Cobley (2): drm/vc4: Correct lbm size and calculation drm/vc4: Correct POS1_SCL for hvs5 Karol Herbst (1): drm/nouveau/svm: fail NOUVEAU_SVM_INIT ioctl on unsupported devices Lyude Paul (3): drivers/nouveau/kms/nv50-: Reject format modifiers for cursor planes drm/nouveau/kms/nv50-: Report max cursor size to userspace drm/nouveau/kms/gk104-gp1xx: Fix > 64x64 cursors Pan Bian (1): drm/i915/selftest: Fix potential memory leak Umesh Nerlige Ramappa (1): drm/i915: Check for all subplatform bits Ville Syrjälä (1): drm/i915: Fix ICL MG PHY vswing handling drivers/gpu/drm/amd/display/dc/dcn30/Makefile | 6 +- drivers/gpu/drm/amd/display/dc/dcn301/Makefile | 3 +- drivers/gpu/drm/amd/display/dc/dcn302/Makefile | 3 +- drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 1 + drivers/gpu/drm/amd/pm/inc/smu_v11_0.h | 3 + drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 9 +- drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 1 + drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 1 + .../drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 1 + drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 31 ++- drivers/gpu/drm/i915/display/intel_ddi.c | 7 +- drivers/gpu/drm/i915/gt/gen7_renderclear.c | 12 ++ drivers/gpu/drm/i915/gt/intel_ggtt.c | 47 +++-- drivers/gpu/drm/i915/i915_active.c | 28 +-- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 2 +- drivers/gpu/drm/nouveau/dispnv50/base507c.c | 6 +- drivers/gpu/drm/nouveau/dispnv50/base827c.c | 6 +- drivers/gpu/drm/nouveau/dispnv50/disp.c | 8 + drivers/gpu/drm/nouveau/dispnv50/head917d.c | 28 ++- drivers/gpu/drm/nouveau/dispnv50/wndw.c | 17 +- .../gpu/drm/nouveau/include/nvhw/class/cl917d.h | 4 + drivers/gpu/drm/nouveau/include/nvif/push.h | 216 ++++++++++----------- drivers/gpu/drm/nouveau/nouveau_svm.c | 4 + drivers/gpu/drm/vc4/vc4_hvs.c | 8 +- drivers/gpu/drm/vc4/vc4_plane.c | 11 +- 26 files changed, 300 insertions(+), 165 deletions(-)

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[GIT PULL] drm/tegra: Changes for v5.12-rc1
by Thierry Reding 29 Jan '21

29 Jan '21

Hi Dave, The following changes since commit 5c8fe583cce542aa0b84adc939ce85293de36e5e: Linux 5.11-rc1 (2020-12-27 15:30:22 -0800) are available in the Git repository at: ssh://git.freedesktop.org/git/tegra/linux.git tags/drm/tegra/for-5.12-rc1 for you to fetch changes up to dcdfe2712b68f1e9dbf4f1a96ad59b80e5cc0ef7: drm/tegra: Fix reference leak when pm_runtime_get_sync() fails (2021-01-15 17:24:51 +0100) Thanks, Thierry ---------------------------------------------------------------- drm/tegra: Changes for v5.12-rc1 Adds support for newer firmware image versions of the Video Image Composer (VIC) and adds a comment clarifying the use of the STREAMID registers. Fixes a couple of issues with display and gr2d on older Tegra SoCs such as Tegra114, as well as a runtime PM reference leak. ---------------------------------------------------------------- Dmitry Osipenko (3): drm/tegra: dc: Enable display controller driver for Tegra114 drm/tegra: gr2d: Correct swapped device-tree compatibles drm/tegra: gr2d: Add compatible for Tegra114 Mikko Perttunen (2): drm/tegra: falcon: Support newer VIC firmware drm/tegra: vic: Add comments on STREAMID registers Qinglang Miao (1): drm/tegra: Fix reference leak when pm_runtime_get_sync() fails drivers/gpu/drm/tegra/dc.c | 2 +- drivers/gpu/drm/tegra/drm.c | 2 ++ drivers/gpu/drm/tegra/dsi.c | 2 +- drivers/gpu/drm/tegra/falcon.c | 9 +++++---- drivers/gpu/drm/tegra/gr2d.c | 9 +++++++-- drivers/gpu/drm/tegra/hdmi.c | 2 +- drivers/gpu/drm/tegra/hub.c | 2 +- drivers/gpu/drm/tegra/sor.c | 2 +- drivers/gpu/drm/tegra/vic.c | 35 ++++++++++++++++++++++++++--------- 9 files changed, 45 insertions(+), 20 deletions(-)

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[PATCH][next] drm/amdgpu: Fix memory leak of object caps on error return paths
by Colin King 29 Jan '21

29 Jan '21

From: Colin Ian King <colin.king(a)canonical.com> Currently there are three error return paths that don't kfree object caps. Fix this by performing the allocation of caps after the checks and error return paths to avoid the premature allocation and memory leaking. Addresses-Coverity: ("Resource leak") Fixes: 555fc7fbb2a2 ("drm/amdgpu: add INFO ioctl support for querying video caps") Signed-off-by: Colin Ian King <colin.king(a)canonical.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 84b666fcfaf6..730f4ac7487b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -988,10 +988,6 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) struct drm_amdgpu_info_video_caps *caps; int r; - caps = kzalloc(sizeof(*caps), GFP_KERNEL); - if (!caps) - return -ENOMEM; - switch (info->video_cap.type) { case AMDGPU_INFO_VIDEO_CAPS_DECODE: r = amdgpu_asic_query_video_codecs(adev, false, &codecs); @@ -1009,6 +1005,11 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) info->video_cap.type); return -EINVAL; } + + caps = kzalloc(sizeof(*caps), GFP_KERNEL); + if (!caps) + return -ENOMEM; + for (i = 0; i < codecs->codec_count; i++) { int idx = codecs->codec_array[i].codec_type; -- 2.29.2

2 1

[PATCH] drm/amd/display: Simplify bool conversion
by Abaci Team 29 Jan '21

29 Jan '21

Fix the following coccicheck warning: ./drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c:3137:35-40: WARNING: conversion to bool not needed here Reported-by: Abaci Robot <abaci(a)linux.alibaba.com> Suggested-by: Yang Li <oswb(a)linux.alibaba.com> Signed-off-by: Abaci Team <abaci-bugfix(a)linux.alibaba.com> --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 017b67b8..fc03d91 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -3134,7 +3134,7 @@ void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc) pipe_ctx->stream_res.opp->funcs->opp_program_stereo( pipe_ctx->stream_res.opp, - flags.PROGRAM_STEREO == 1 ? true:false, + flags.PROGRAM_STEREO == 1, &stream->timing); pipe_ctx->stream_res.tg->funcs->program_stereo( -- 1.8.3.1

2 1

[PATCH AUTOSEL 5.4 16/19] drm/amd/display: Change function decide_dp_link_settings to avoid infinite looping
by Sasha Levin 29 Jan '21

29 Jan '21

From: Bing Guo <bing.guo(a)amd.com> [ Upstream commit 4716a7c50c5c66d6ddc42401e1e0ba13b492e105 ] Why: Function decide_dp_link_settings() loops infinitely when required bandwidth can't be supported. How: Check the required bandwidth against verified_link_cap before trying to find a link setting for it. Tested-by: Daniel Wheeler <daniel.wheeler(a)amd.com> Signed-off-by: Bing Guo <bing.guo(a)amd.com> Reviewed-by: Jun Lei <Jun.Lei(a)amd.com> Acked-by: Anson Jacob <anson.jacob(a)amd.com> Signed-off-by: Alex Deucher <alexander.deucher(a)amd.com> Signed-off-by: Sasha Levin <sashal(a)kernel.org> --- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index 959eb075d11ed..c18f39271b034 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -1914,6 +1914,9 @@ static bool decide_dp_link_settings(struct dc_link *link, struct dc_link_setting initial_link_setting; uint32_t link_bw; + if (req_bw > dc_link_bandwidth_kbps(link, &link->verified_link_cap)) + return false; + /* search for the minimum link setting that: * 1. is supported according to the link training result * 2. could support the b/w requested by the timing -- 2.27.0

1 0

[PATCH AUTOSEL 5.4 15/19] drm/amd/display: Update dram_clock_change_latency for DCN2.1
by Sasha Levin 29 Jan '21

29 Jan '21

From: Jake Wang <haonan.wang2(a)amd.com> [ Upstream commit 901c1ec05ef277ce9d43cb806a225b28b3efe89a ] [WHY] dram clock change latencies get updated using ddr4 latency table, but does that update does not happen before validation. This value should not be the default and should be number received from df for better mode support. This may cause a PState hang on high refresh panels with short vblanks such as on 1080p 360hz or 300hz panels. [HOW] Update latency from 23.84 to 11.72. Signed-off-by: Sung Lee <sung.lee(a)amd.com> Reviewed-by: Tony Cheng <Tony.Cheng(a)amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai(a)amd.com> Signed-off-by: Alex Deucher <alexander.deucher(a)amd.com> Signed-off-by: Sasha Levin <sashal(a)kernel.org> --- drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c index bb7add5ea2273..a6d5beada6634 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c @@ -257,7 +257,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = { .num_banks = 8, .num_chans = 4, .vmm_page_size_bytes = 4096, - .dram_clock_change_latency_us = 23.84, + .dram_clock_change_latency_us = 11.72, .return_bus_width_bytes = 64, .dispclk_dppclk_vco_speed_mhz = 3600, .xfc_bus_transport_time_us = 4, -- 2.27.0

1 0

[PATCH AUTOSEL 5.10 33/41] drm/amd/display: Fixed corruptions on HPDRX link loss restore
by Sasha Levin 29 Jan '21

29 Jan '21

From: Vladimir Stempen <vladimir.stempen(a)amd.com> [ Upstream commit 4b08d8c78360241d270396a9de6eb774e88acd00 ] [why] Heavy corruption or blank screen reported on wake, with 6k display connected and FEC enabled [how] When Disable/Enable stream for display pipes on HPDRX, DC should take into account ODM split pipes. Tested-by: Daniel Wheeler <daniel.wheeler(a)amd.com> Signed-off-by: Vladimir Stempen <vladimir.stempen(a)amd.com> Reviewed-by: Aric Cyr <Aric.Cyr(a)amd.com> Acked-by: Anson Jacob <anson.jacob(a)amd.com> Signed-off-by: Alex Deucher <alexander.deucher(a)amd.com> Signed-off-by: Sasha Levin <sashal(a)kernel.org> --- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index 004e2b32e02fa..17e6fd8201395 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -3023,14 +3023,14 @@ bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd for (i = 0; i < MAX_PIPES; i++) { pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i]; if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off && - pipe_ctx->stream->link == link) + pipe_ctx->stream->link == link && !pipe_ctx->prev_odm_pipe) core_link_disable_stream(pipe_ctx); } for (i = 0; i < MAX_PIPES; i++) { pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i]; if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off && - pipe_ctx->stream->link == link) + pipe_ctx->stream->link == link && !pipe_ctx->prev_odm_pipe) core_link_enable_stream(link->dc->current_state, pipe_ctx); } -- 2.27.0

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dri-devel January 2021