Trying to run AMD E9260 (Polaris 11) on NXP LS1012A-RDB
bas at daedalean.ai
Thu Jan 10 13:31:24 UTC 2019
On Thu, Jan 10, 2019 at 11:59 AM Christian König <
ckoenig.leichtzumerken at gmail.com> wrote:
> The PCI Express controller as instantiated on this chip does not support
> hardware coherency. All incoming PCI Express transactions are made non
> Would AMDGPU still work with that PCI Express controller, or is this a
> I'm really wondering what this comment in the documentation means.
> As far as I know PCIe doesn't support cache coherency in the downstream
> and supporting it in the up stream is a must have.
So what exactly is meant here with IO-coherent?
I believe IO Coherent means that when PCIe writes something to CPU memory,
the caches are flushed or updated
(or in this case they aren't). I found
with this explanation.
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