[Mesa-dev] [PATCH 08/51] i965: Rename intel_batchbuffer to brw_batch
Chris Wilson
chris at chris-wilson.co.uk
Tue Jan 10 21:23:31 UTC 2017
In order to reduce future churn, rename the intel_batchbuffer struct.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
---
src/mesa/drivers/dri/i965/brw_batch.h | 4 ++--
src/mesa/drivers/dri/i965/brw_context.h | 2 +-
src/mesa/drivers/dri/i965/brw_state_batch.c | 6 ++----
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 16 ++++++++--------
src/mesa/drivers/dri/i965/intel_batchbuffer.h | 18 +++++++++---------
5 files changed, 22 insertions(+), 24 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_batch.h b/src/mesa/drivers/dri/i965/brw_batch.h
index a1307c1a0e..d6feb3ca5f 100644
--- a/src/mesa/drivers/dri/i965/brw_batch.h
+++ b/src/mesa/drivers/dri/i965/brw_batch.h
@@ -41,7 +41,7 @@ enum brw_gpu_ring {
BLT_RING,
};
-struct intel_batchbuffer {
+typedef struct brw_batch {
/** Current batchbuffer being queued up. */
brw_bo *bo;
/** Last BO submitted to the hardware. Used for glFinish(). */
@@ -65,7 +65,7 @@ struct intel_batchbuffer {
uint32_t *map_next;
int reloc_count;
} saved;
-};
+} brw_batch;
#ifdef __cplusplus
}
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index a4c963acde..c7c25a7274 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -715,7 +715,7 @@ struct brw_context
*/
uint32_t reset_count;
- struct intel_batchbuffer batch;
+ brw_batch batch;
bool no_batch_wrap;
struct {
diff --git a/src/mesa/drivers/dri/i965/brw_state_batch.c b/src/mesa/drivers/dri/i965/brw_state_batch.c
index 8cff0b6d1f..f3fc51e8c1 100644
--- a/src/mesa/drivers/dri/i965/brw_state_batch.c
+++ b/src/mesa/drivers/dri/i965/brw_state_batch.c
@@ -40,15 +40,13 @@ brw_track_state_batch(struct brw_context *brw,
int size,
int index)
{
- struct intel_batchbuffer *batch = &brw->batch;
-
if (!brw->state_batch_list) {
/* Our structs are always aligned to at least 32 bytes, so
* our array doesn't need to be any larger
* TODO: don't use rzalloc
*/
brw->state_batch_list = rzalloc_size(brw, sizeof(*brw->state_batch_list) *
- batch->bo->size / 32);
+ brw->batch.bo->size / 32);
}
brw->state_batch_list[brw->state_batch_count].offset = offset;
@@ -125,7 +123,7 @@ __brw_state_batch(struct brw_context *brw,
uint32_t *out_offset)
{
- struct intel_batchbuffer *batch = &brw->batch;
+ brw_batch *batch = &brw->batch;
uint32_t offset;
assert(size < batch->bo->size);
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index aaa02d3df7..5e123eb9a6 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -37,11 +37,11 @@
#include <i915_drm.h>
static void
-intel_batchbuffer_reset(struct intel_batchbuffer *batch, dri_bufmgr *bufmgr,
+intel_batchbuffer_reset(struct brw_batch *batch, dri_bufmgr *bufmgr,
bool has_llc);
void
-intel_batchbuffer_init(struct intel_batchbuffer *batch, dri_bufmgr *bufmgr,
+intel_batchbuffer_init(struct brw_batch *batch, dri_bufmgr *bufmgr,
bool has_llc)
{
intel_batchbuffer_reset(batch, bufmgr, has_llc);
@@ -54,7 +54,7 @@ intel_batchbuffer_init(struct intel_batchbuffer *batch, dri_bufmgr *bufmgr,
}
static void
-intel_batchbuffer_reset(struct intel_batchbuffer *batch, dri_bufmgr *bufmgr,
+intel_batchbuffer_reset(struct brw_batch *batch, dri_bufmgr *bufmgr,
bool has_llc)
{
if (batch->last_bo != NULL) {
@@ -107,7 +107,7 @@ intel_batchbuffer_reset_to_saved(struct brw_context *brw)
}
void
-intel_batchbuffer_free(struct intel_batchbuffer *batch)
+intel_batchbuffer_free(struct brw_batch *batch)
{
free(batch->cpu_map);
drm_intel_bo_unreference(batch->last_bo);
@@ -144,7 +144,7 @@ static void
do_batch_dump(struct brw_context *brw)
{
struct drm_intel_decode *decode;
- struct intel_batchbuffer *batch = &brw->batch;
+ brw_batch *batch = &brw->batch;
int ret;
decode = drm_intel_decode_context_alloc(brw->screen->deviceID);
@@ -322,7 +322,7 @@ throttle(struct brw_context *brw)
static int
do_flush_locked(struct brw_context *brw)
{
- struct intel_batchbuffer *batch = &brw->batch;
+ brw_batch *batch = &brw->batch;
int ret = 0;
if (brw->has_llc) {
@@ -440,7 +440,7 @@ _intel_batchbuffer_flush(struct brw_context *brw,
/* This is the only way buffers get added to the validate list.
*/
uint32_t
-intel_batchbuffer_reloc(struct intel_batchbuffer *batch,
+intel_batchbuffer_reloc(struct brw_batch *batch,
brw_bo *buffer, uint32_t offset,
uint32_t read_domains, uint32_t write_domain,
uint32_t delta)
@@ -461,7 +461,7 @@ intel_batchbuffer_reloc(struct intel_batchbuffer *batch,
}
uint64_t
-intel_batchbuffer_reloc64(struct intel_batchbuffer *batch,
+intel_batchbuffer_reloc64(struct brw_batch *batch,
brw_bo *buffer, uint32_t offset,
uint32_t read_domains, uint32_t write_domain,
uint32_t delta)
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.h b/src/mesa/drivers/dri/i965/intel_batchbuffer.h
index 04650a7d0f..eb8be9657c 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.h
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.h
@@ -40,14 +40,14 @@ extern "C" {
*/
#define BATCH_RESERVED 308
-struct intel_batchbuffer;
+struct brw_batch;
struct brw_context;
enum brw_gpu_ring;
void intel_batchbuffer_emit_render_ring_prelude(struct brw_context *brw);
-void intel_batchbuffer_init(struct intel_batchbuffer *batch, dri_bufmgr *bufmgr,
+void intel_batchbuffer_init(struct brw_batch *batch, dri_bufmgr *bufmgr,
bool has_llc);
-void intel_batchbuffer_free(struct intel_batchbuffer *batch);
+void intel_batchbuffer_free(struct brw_batch *batch);
void intel_batchbuffer_save_state(struct brw_context *brw);
void intel_batchbuffer_reset_to_saved(struct brw_context *brw);
void intel_batchbuffer_require_space(struct brw_context *brw, GLuint sz,
@@ -69,13 +69,13 @@ void intel_batchbuffer_data(struct brw_context *brw,
const void *data, GLuint bytes,
enum brw_gpu_ring ring);
-uint32_t intel_batchbuffer_reloc(struct intel_batchbuffer *batch,
+uint32_t intel_batchbuffer_reloc(struct brw_batch *batch,
brw_bo *buffer,
uint32_t offset,
uint32_t read_domains,
uint32_t write_domain,
uint32_t delta);
-uint64_t intel_batchbuffer_reloc64(struct intel_batchbuffer *batch,
+uint64_t intel_batchbuffer_reloc64(struct brw_batch *batch,
brw_bo *buffer,
uint32_t offset,
uint32_t read_domains,
@@ -101,7 +101,7 @@ static inline uint32_t float_as_int(float f)
* work...
*/
static inline unsigned
-intel_batchbuffer_space(struct intel_batchbuffer *batch)
+intel_batchbuffer_space(struct brw_batch *batch)
{
return (batch->state_batch_offset - batch->reserved_space)
- USED_BATCH(*batch) * 4;
@@ -109,7 +109,7 @@ intel_batchbuffer_space(struct intel_batchbuffer *batch)
static inline void
-intel_batchbuffer_emit_dword(struct intel_batchbuffer *batch, GLuint dword)
+intel_batchbuffer_emit_dword(struct brw_batch *batch, GLuint dword)
{
#ifdef DEBUG
assert(intel_batchbuffer_space(batch) >= 4);
@@ -119,7 +119,7 @@ intel_batchbuffer_emit_dword(struct intel_batchbuffer *batch, GLuint dword)
}
static inline void
-intel_batchbuffer_emit_float(struct intel_batchbuffer *batch, float f)
+intel_batchbuffer_emit_float(struct brw_batch *batch, float f)
{
intel_batchbuffer_emit_dword(batch, float_as_int(f));
}
@@ -139,7 +139,7 @@ static inline void
intel_batchbuffer_advance(struct brw_context *brw)
{
#ifdef DEBUG
- struct intel_batchbuffer *batch = &brw->batch;
+ brw_batch *batch = &brw->batch;
unsigned int _n = USED_BATCH(*batch) - batch->emit;
assert(batch->total != 0);
if (_n != batch->total) {
--
2.11.0
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