dri-devel April 2021

dri-devel@lists.freedesktop.org

317 participants
715 discussions

[PATCH 1/2] drm/msm/dp: service only one irq_hpd if there are multiple irq_hpd pending
by Kuogee Hsieh 04 May '21

04 May '21

Some dongle may generate more than one irq_hpd events in a short period of time. This patch will treat those irq_hpd events as single one and service only one irq_hpd event. Signed-off-by: Kuogee Hsieh <khsieh(a)codeaurora.org> --- drivers/gpu/drm/msm/dp/dp_display.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index 5a39da6..0a7d383 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -707,6 +707,9 @@ static int dp_irq_hpd_handle(struct dp_display_private *dp, u32 data) return 0; } + /* only handle first irq_hpd in case of multiple irs_hpd pending */ + dp_del_event(dp, EV_IRQ_HPD_INT); + ret = dp_display_usbpd_attention_cb(&dp->pdev->dev); if (ret == -ECONNRESET) { /* cable unplugged */ dp->core_initialized = false; @@ -1300,6 +1303,9 @@ static int dp_pm_suspend(struct device *dev) /* host_init will be called at pm_resume */ dp->core_initialized = false; + /* system suspended, delete pending irq_hdps */ + dp_del_event(dp, EV_IRQ_HPD_INT); + mutex_unlock(&dp->event_mutex); return 0; @@ -1496,6 +1502,9 @@ int msm_dp_display_disable(struct msm_dp *dp, struct drm_encoder *encoder) /* stop sentinel checking */ dp_del_event(dp_display, EV_DISCONNECT_PENDING_TIMEOUT); + /* link is down, delete pending irq_hdps */ + dp_del_event(dp_display, EV_IRQ_HPD_INT); + dp_display_disable(dp_display, 0); rc = dp_display_unprepare(dp); -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project

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[RESEND PATCH v6 1/4] mfd: rt4831: Adds support for Richtek RT4831
by cy_huang 04 May '21

04 May '21

From: ChiYuan Huang <cy_huang(a)richtek.com> This adds support Richtek RT4831 core. It includes four channel WLED driver and Display Bias Voltage outputs. Signed-off-by: ChiYuan Huang <cy_huang(a)richtek.com> --- Resend this v6 patch series to loop devicetree reviewers. The RT4831 regulator patches are already on main stream, and can be referred to 9351ab8b0cb6 regulator: rt4831: Adds support for Richtek RT4831 DSV regulator 934b05e81862 regulator: rt4831: Adds DT binding document for Richtek RT4831 DSV regulator since v6 - Respin the date from 2020 to 2021. - Rmove the shutdown routine. - Change the macro OF_MFD_CELL to MFD_CELL_OF. since v5 - Rename file name from rt4831-core.c to rt4831.c - Change RICHTEK_VID to RICHTEK_VENDOR_ID. - Change gpio_desc nameing from 'enable' to 'enable_gpio' in probe. - Change variable 'val' to the meaningful name 'chip_id'. - Refine the error log when vendor id is not matched. - Remove of_match_ptr. since v2 - Refine Kconfig descriptions. - Add copyright. - Refine error logs in probe. - Refine comment lines in remove and shutdown. --- drivers/mfd/Kconfig | 10 +++++ drivers/mfd/Makefile | 1 + drivers/mfd/rt4831.c | 115 +++++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 126 insertions(+) create mode 100644 drivers/mfd/rt4831.c diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index b74efa4..3f43834 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -1065,6 +1065,16 @@ config MFD_RDC321X southbridge which provides access to GPIOs and Watchdog using the southbridge PCI device configuration space. +config MFD_RT4831 + tristate "Richtek RT4831 four channel WLED and Display Bias Voltage" + depends on I2C + select MFD_CORE + select REGMAP_I2C + help + This enables support for the Richtek RT4831 that includes 4 channel + WLED driving and Display Bias Voltage. It's commonly used to provide + power to the LCD display and LCD backlight. + config MFD_RT5033 tristate "Richtek RT5033 Power Management IC" depends on I2C diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index 834f546..5986914 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -235,6 +235,7 @@ obj-$(CONFIG_MFD_MENF21BMC) += menf21bmc.o obj-$(CONFIG_MFD_HI6421_PMIC) += hi6421-pmic-core.o obj-$(CONFIG_MFD_HI655X_PMIC) += hi655x-pmic.o obj-$(CONFIG_MFD_DLN2) += dln2.o +obj-$(CONFIG_MFD_RT4831) += rt4831.o obj-$(CONFIG_MFD_RT5033) += rt5033.o obj-$(CONFIG_MFD_SKY81452) += sky81452.o diff --git a/drivers/mfd/rt4831.c b/drivers/mfd/rt4831.c new file mode 100644 index 00000000..b169781 --- /dev/null +++ b/drivers/mfd/rt4831.c @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2021 Richtek Technology Corp. + * + * Author: ChiYuan Huang <cy_huang(a)richtek.com> + */ + +#include <linux/gpio/consumer.h> +#include <linux/i2c.h> +#include <linux/kernel.h> +#include <linux/mfd/core.h> +#include <linux/module.h> +#include <linux/regmap.h> + +#define RT4831_REG_REVISION 0x01 +#define RT4831_REG_ENABLE 0x08 +#define RT4831_REG_I2CPROT 0x15 + +#define RICHTEK_VENDOR_ID 0x03 +#define RT4831_VID_MASK GENMASK(1, 0) +#define RT4831_RESET_MASK BIT(7) +#define RT4831_I2CSAFETMR_MASK BIT(0) + +static const struct mfd_cell rt4831_subdevs[] = { + MFD_CELL_OF("rt4831-backlight", NULL, NULL, 0, 0, "richtek,rt4831-backlight"), + MFD_CELL_NAME("rt4831-regulator") +}; + +static bool rt4831_is_accessible_reg(struct device *dev, unsigned int reg) +{ + if (reg >= RT4831_REG_REVISION && reg <= RT4831_REG_I2CPROT) + return true; + return false; +} + +static const struct regmap_config rt4831_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .max_register = RT4831_REG_I2CPROT, + + .readable_reg = rt4831_is_accessible_reg, + .writeable_reg = rt4831_is_accessible_reg, +}; + +static int rt4831_probe(struct i2c_client *client) +{ + struct gpio_desc *enable_gpio; + struct regmap *regmap; + unsigned int chip_id; + int ret; + + enable_gpio = devm_gpiod_get_optional(&client->dev, "enable", GPIOD_OUT_HIGH); + if (IS_ERR(enable_gpio)) { + dev_err(&client->dev, "Failed to get 'enable' GPIO\n"); + return PTR_ERR(enable_gpio); + } + + regmap = devm_regmap_init_i2c(client, &rt4831_regmap_config); + if (IS_ERR(regmap)) { + dev_err(&client->dev, "Failed to initialize regmap\n"); + return PTR_ERR(regmap); + } + + ret = regmap_read(regmap, RT4831_REG_REVISION, &chip_id); + if (ret) { + dev_err(&client->dev, "Failed to get H/W revision\n"); + return ret; + } + + if ((chip_id & RT4831_VID_MASK) != RICHTEK_VENDOR_ID) { + dev_err(&client->dev, "Chip vendor ID 0x%02x not matched\n", chip_id); + return -ENODEV; + } + + /* + * Used to prevent the abnormal shutdown. + * If SCL/SDA both keep low for one second to reset HW. + */ + ret = regmap_update_bits(regmap, RT4831_REG_I2CPROT, RT4831_I2CSAFETMR_MASK, + RT4831_I2CSAFETMR_MASK); + if (ret) { + dev_err(&client->dev, "Failed to enable I2C safety timer\n"); + return ret; + } + + return devm_mfd_add_devices(&client->dev, PLATFORM_DEVID_AUTO, rt4831_subdevs, + ARRAY_SIZE(rt4831_subdevs), NULL, 0, NULL); +} + +static int rt4831_remove(struct i2c_client *client) +{ + struct regmap *regmap = dev_get_regmap(&client->dev, NULL); + + /* Disable WLED and DSV outputs */ + return regmap_update_bits(regmap, RT4831_REG_ENABLE, RT4831_RESET_MASK, RT4831_RESET_MASK); +} + +static const struct of_device_id __maybe_unused rt4831_of_match[] = { + { .compatible = "richtek,rt4831", }, + {} +}; +MODULE_DEVICE_TABLE(of, rt4831_of_match); + +static struct i2c_driver rt4831_driver = { + .driver = { + .name = "rt4831", + .of_match_table = rt4831_of_match, + }, + .probe_new = rt4831_probe, + .remove = rt4831_remove, +}; +module_i2c_driver(rt4831_driver); + +MODULE_AUTHOR("ChiYuan Huang <cy_huang(a)richtek.com>"); +MODULE_LICENSE("GPL v2"); -- 2.7.4

4 10

[PATCH] dt-bindings: display: renesas, du: Add missing power-domains property
by Geert Uytterhoeven 03 May '21

03 May '21

"make dtbs_check" complains: arch/arm/boot/dts/r8a7779-marzen.dt.yaml: display@fff80000: 'power-domains' does not match any of the regexes: 'pinctrl-[0-9]+' arch/arm64/boot/dts/renesas/r8a77970-v3msk.dt.yaml: display@feb00000: 'power-domains' does not match any of the regexes: 'pinctrl-[0-9]+' arch/arm64/boot/dts/renesas/r8a77970-eagle.dt.yaml: display@feb00000: 'power-domains' does not match any of the regexes: 'pinctrl-[0-9]+' arch/arm64/boot/dts/renesas/r8a77980-condor.dt.yaml: display@feb00000: 'power-domains' does not match any of the regexes: 'pinctrl-[0-9]+' arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dt.yaml: display@feb00000: 'power-domains' does not match any of the regexes: 'pinctrl-[0-9]+' Fix this by documenting the power-domains property. Fixes: 99d66127fad25ebb ("dt-bindings: display: renesas,du: Convert binding to YAML") Signed-off-by: Geert Uytterhoeven <geert+renesas(a)glider.be> --- Documentation/devicetree/bindings/display/renesas,du.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/display/renesas,du.yaml b/Documentation/devicetree/bindings/display/renesas,du.yaml index e955034da53b86e2..0dad87cdd8735542 100644 --- a/Documentation/devicetree/bindings/display/renesas,du.yaml +++ b/Documentation/devicetree/bindings/display/renesas,du.yaml @@ -51,6 +51,9 @@ properties: resets: true reset-names: true + power-domains: + maxItems: 1 + ports: $ref: /schemas/graph.yaml#/properties/port description: | -- 2.25.1

4 3

[PATCH 0/1] Add support for querying engine cycles
by Umesh Nerlige Ramappa 03 May '21

03 May '21

This is just a refresh of the earlier patch along with cover letter for the IGT testing. The query provides the engine cs cycles counter. v2: Use GRAPHICS_VER() instead of IG_GEN() v3: Add R-b to the patch v4: Split cpu timestamp array into timestamp and delta for cleaner API Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa(a)intel.com> Test-with: 20210429002959.69473-1-umesh.nerlige.ramappa(a)intel.com Umesh Nerlige Ramappa (1): i915/query: Correlate engine and cpu timestamps with better accuracy drivers/gpu/drm/i915/i915_query.c | 148 ++++++++++++++++++++++++++++++ include/uapi/drm/i915_drm.h | 52 +++++++++++ 2 files changed, 200 insertions(+) -- 2.20.1

4 11

[PATCH v3 0/4] staging: fbtft: Fixing GPIO handling issues
by Andy Shevchenko 03 May '21

03 May '21

This series fixes a number of GPIO handling issues after converting this driver to use descriptors. The series has been tested on HX8347d display with parallel interface. Without first patch it's not working. In v3: - added staging prefix (Fabio) - slightly amended commit message in the patch 1 - added Rb tag (Phil) - dropped Fixes tag from the patch 2 (Greg) Andy Shevchenko (4): staging: fbtft: Rectify GPIO handling staging: fbtft: Replace custom ->reset() with generic one staging: fbtft: Don't spam logs when probe is deferred staging: fbtft: Update TODO drivers/staging/fbtft/TODO | 5 ----- drivers/staging/fbtft/fb_agm1264k-fl.c | 30 +++++++------------------- drivers/staging/fbtft/fb_bd663474.c | 4 ---- drivers/staging/fbtft/fb_ili9163.c | 4 ---- drivers/staging/fbtft/fb_ili9320.c | 1 - drivers/staging/fbtft/fb_ili9325.c | 4 ---- drivers/staging/fbtft/fb_ili9340.c | 1 - drivers/staging/fbtft/fb_s6d1121.c | 4 ---- drivers/staging/fbtft/fb_sh1106.c | 1 - drivers/staging/fbtft/fb_ssd1289.c | 4 ---- drivers/staging/fbtft/fb_ssd1325.c | 2 -- drivers/staging/fbtft/fb_ssd1331.c | 6 ++---- drivers/staging/fbtft/fb_ssd1351.c | 1 - drivers/staging/fbtft/fb_upd161704.c | 4 ---- drivers/staging/fbtft/fb_watterott.c | 1 - drivers/staging/fbtft/fbtft-bus.c | 3 +-- drivers/staging/fbtft/fbtft-core.c | 25 +++++++++------------ drivers/staging/fbtft/fbtft-io.c | 12 +++++------ 18 files changed, 27 insertions(+), 85 deletions(-) -- 2.30.2

4 9

[PATCH] drm/i915/display Try YCbCr420 color when RGB fails
by Werner Sembach 03 May '21

03 May '21

When encoder validation of a display mode fails, retry with less bandwidth heavy YCbCr420 color mode, if available. This enables some HDMI 1.4 setups to support 4k60Hz output, which previously failed silently. AMDGPU had nearly the exact same issue. This problem description is therefore copied from my commit message of the AMDGPU patch. On some setups, while the monitor and the gpu support display modes with pixel clocks of up to 600MHz, the link encoder might not. This prevents YCbCr444 and RGB encoding for 4k60Hz, but YCbCr420 encoding might still be possible. However, which color mode is used is decided before the link encoder capabilities are checked. This patch fixes the problem by retrying to find a display mode with YCbCr420 enforced and using it, if it is valid. I'm not entierly sure if the second "if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))" check in intel_hdmi_compute_config(...) after forcing ycbcr420 is necessary. I included it to better be safe then sorry. Signed-off-by: Werner Sembach <wse(a)tuxedocomputers.com> Cc: <stable(a)vger.kernel.org> --- Rebased from 5.12 to drm-tip and resend to resolve merge conflict. >From 876c1c8d970ff2a411ee8d08651bd4edbe9ecb3d Mon Sep 17 00:00:00 2001 From: Werner Sembach <wse(a)tuxedocomputers.com> Date: Thu, 29 Apr 2021 13:59:30 +0200 Subject: [PATCH] Retry using YCbCr420 encoding if clock setup for RGB fails --- drivers/gpu/drm/i915/display/intel_hdmi.c | 80 +++++++++++++++++------ 1 file changed, 60 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index 46de56af33db..c9b5a7d7f9c6 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -1861,6 +1861,30 @@ static int intel_hdmi_port_clock(int clock, int bpc) return clock * bpc / 8; } +static enum drm_mode_status +intel_hdmi_check_bpc(struct intel_hdmi *hdmi, int clock, bool has_hdmi_sink, struct drm_i915_private *dev_priv) +{ + enum drm_mode_status status; + + /* check if we can do 8bpc */ + status = hdmi_port_clock_valid(hdmi, intel_hdmi_port_clock(clock, 8), + true, has_hdmi_sink); + + if (has_hdmi_sink) { + /* if we can't do 8bpc we may still be able to do 12bpc */ + if (status != MODE_OK && !HAS_GMCH(dev_priv)) + status = hdmi_port_clock_valid(hdmi, intel_hdmi_port_clock(clock, 12), + true, has_hdmi_sink); + + /* if we can't do 8,12bpc we may still be able to do 10bpc */ + if (status != MODE_OK && DISPLAY_VER(dev_priv) >= 11) + status = hdmi_port_clock_valid(hdmi, intel_hdmi_port_clock(clock, 10), + true, has_hdmi_sink); + } + + return status; +} + static enum drm_mode_status intel_hdmi_mode_valid(struct drm_connector *connector, struct drm_display_mode *mode) @@ -1891,23 +1915,18 @@ intel_hdmi_mode_valid(struct drm_connector *connector, if (drm_mode_is_420_only(&connector->display_info, mode)) clock /= 2; - /* check if we can do 8bpc */ - status = hdmi_port_clock_valid(hdmi, intel_hdmi_port_clock(clock, 8), - true, has_hdmi_sink); + status = intel_hdmi_check_bpc(hdmi, clock, has_hdmi_sink, dev_priv); - if (has_hdmi_sink) { - /* if we can't do 8bpc we may still be able to do 12bpc */ - if (status != MODE_OK && !HAS_GMCH(dev_priv)) - status = hdmi_port_clock_valid(hdmi, intel_hdmi_port_clock(clock, 12), - true, has_hdmi_sink); + if (status != MODE_OK) { + if (drm_mode_is_420_also(&connector->display_info, mode)) { + /* if we can't do full color resolution we may still be able to do reduced color resolution */ + clock /= 2; - /* if we can't do 8,12bpc we may still be able to do 10bpc */ - if (status != MODE_OK && DISPLAY_VER(dev_priv) >= 11) - status = hdmi_port_clock_valid(hdmi, intel_hdmi_port_clock(clock, 10), - true, has_hdmi_sink); + status = intel_hdmi_check_bpc(hdmi, clock, has_hdmi_sink, dev_priv); + } + if (status != MODE_OK) + return status; } - if (status != MODE_OK) - return status; return intel_mode_valid_max_plane_size(dev_priv, mode, false); } @@ -1990,14 +2009,17 @@ static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state, static int intel_hdmi_ycbcr420_config(struct intel_crtc_state *crtc_state, - const struct drm_connector_state *conn_state) + const struct drm_connector_state *conn_state, + const bool force_ycbcr420) { struct drm_connector *connector = conn_state->connector; struct drm_i915_private *i915 = to_i915(connector->dev); const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; - if (!drm_mode_is_420_only(&connector->display_info, adjusted_mode)) + if (!(drm_mode_is_420_only(&connector->display_info, adjusted_mode) || + (force_ycbcr420 && + drm_mode_is_420_also(&connector->display_info, adjusted_mode)))) return 0; if (!connector->ycbcr_420_allowed) { @@ -2126,7 +2148,7 @@ int intel_hdmi_compute_config(struct intel_encoder *encoder, struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; struct drm_connector *connector = conn_state->connector; struct drm_scdc *scdc = &connector->display_info.hdmi.scdc; - int ret; + int ret, ret_saved; if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) return -EINVAL; @@ -2141,7 +2163,7 @@ int intel_hdmi_compute_config(struct intel_encoder *encoder, if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) pipe_config->pixel_multiplier = 2; - ret = intel_hdmi_ycbcr420_config(pipe_config, conn_state); + ret = intel_hdmi_ycbcr420_config(pipe_config, conn_state, false); if (ret) return ret; @@ -2155,8 +2177,26 @@ int intel_hdmi_compute_config(struct intel_encoder *encoder, intel_hdmi_has_audio(encoder, pipe_config, conn_state); ret = intel_hdmi_compute_clock(encoder, pipe_config); - if (ret) - return ret; + if (ret) { + ret_saved = ret; + + ret = intel_hdmi_ycbcr420_config(pipe_config, conn_state, true); + if (ret) + return ret; + + if (pipe_config->output_format != INTEL_OUTPUT_FORMAT_YCBCR420) + return ret_saved; + + pipe_config->limited_color_range = + intel_hdmi_limited_color_range(pipe_config, conn_state); + + if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv)) + pipe_config->has_pch_encoder = true; + + ret = intel_hdmi_compute_clock(encoder, pipe_config); + if (ret) + return ret; + } if (conn_state->picture_aspect_ratio) adjusted_mode->picture_aspect_ratio = -- 2.25.1

2 3

Display notch support
by Caleb Connolly 03 May '21

03 May '21

With many more non-desktop form factor devices landing in the kernel, we're starting to run up against some limitations. Notably devices with display notches, cutouts and rounded corners. Given that the DRI subsystem already deals with physical display properties like panel orientation which is fixed in device tree, it would make sense to also define other properties like parts of the display which are obscured there too. This can then be read by desktop environments and UI elements can be suitably adjusted. Android already deals with non-square displays, however they also keep the device configuration in userspace: https://developer.android.com/guide/topics/display-cutout A solution to make this configuration generic and exposed by the kernel would standardise this across Linux and potentially Android too which would be extremely beneficial to the mobile Linux community at large. Does this seem like a feasible solution to solving the notch problem and avoiding a situation where every compositor have their own method of describing cutouts and rounded corners? Regards, Caleb

5 6

[PATCH v2 0/1] drm/i915: Use the correct max source link rate for MST
by Nikola Cornij 03 May '21

03 May '21

This is a follow-up change to fix incorrectly used max link rate source capability at MST init time. Change history: v1: - Initial v2: - Use local variabale for improved code readability - Fix the comment to point to the correct sub-directory Nikola Cornij (1): drm/i915: Use the correct max source link rate for MST drivers/gpu/drm/i915/display/intel_dp_mst.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -- 2.25.1

4 4

[PATCH] drm/msm/dpu: Delete bonkers code
by Rob Clark 03 May '21

03 May '21

From: Rob Clark <robdclark(a)chromium.org> dpu_crtc_atomic_flush() was directly poking it's attached planes in a code path that ended up in dpu_plane_atomic_update(), even if the plane was not involved in the current atomic update. While a bit dubious, this worked before because plane->state would always point to something valid. But now using drm_atomic_get_new_plane_state() we could get a NULL state pointer instead, leading to: [ 20.873273] Call trace: [ 20.875740] dpu_plane_atomic_update+0x5c/0xed0 [ 20.880311] dpu_plane_restore+0x40/0x88 [ 20.884266] dpu_crtc_atomic_flush+0xf4/0x208 [ 20.888660] drm_atomic_helper_commit_planes+0x150/0x238 [ 20.894014] msm_atomic_commit_tail+0x1d4/0x7a0 [ 20.898579] commit_tail+0xa4/0x168 [ 20.902102] drm_atomic_helper_commit+0x164/0x178 [ 20.906841] drm_atomic_commit+0x54/0x60 [ 20.910798] drm_atomic_connector_commit_dpms+0x10c/0x118 [ 20.916236] drm_mode_obj_set_property_ioctl+0x1e4/0x440 [ 20.921588] drm_connector_property_set_ioctl+0x60/0x88 [ 20.926852] drm_ioctl_kernel+0xd0/0x120 [ 20.930807] drm_ioctl+0x21c/0x478 [ 20.934235] __arm64_sys_ioctl+0xa8/0xe0 [ 20.938193] invoke_syscall+0x64/0x130 [ 20.941977] el0_svc_common.constprop.3+0x5c/0xe0 [ 20.946716] do_el0_svc+0x80/0xa0 [ 20.950058] el0_svc+0x20/0x30 [ 20.953145] el0_sync_handler+0x88/0xb0 [ 20.957014] el0_sync+0x13c/0x140 The reason for the codepath seems dubious, the atomic suspend/resume heplers should handle the power-collapse case. If not, the CRTC's atomic_check() should be adding the planes to the atomic update. Reported-by: Stephen Boyd <sboyd(a)kernel.org> Reported-by: John Stultz <john.stultz(a)linaro.org> Fixes: 37418bf14c13 drm: Use state helper instead of the plane state pointer Signed-off-by: Rob Clark <robdclark(a)chromium.org> --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 10 ---------- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 16 ---------------- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 6 ------ 3 files changed, 32 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 7c29976be243..18bc76b7f1a3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -648,16 +648,6 @@ static void dpu_crtc_atomic_flush(struct drm_crtc *crtc, if (unlikely(!cstate->num_mixers)) return; - /* - * For planes without commit update, drm framework will not add - * those planes to current state since hardware update is not - * required. However, if those planes were power collapsed since - * last commit cycle, driver has to restore the hardware state - * of those planes explicitly here prior to plane flush. - */ - drm_atomic_crtc_for_each_plane(plane, crtc) - dpu_plane_restore(plane, state); - /* update performance setting before crtc kickoff */ dpu_core_perf_crtc_update(crtc, 1, false); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index df7f3d3afd8b..7a993547eb75 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -1258,22 +1258,6 @@ static void dpu_plane_atomic_update(struct drm_plane *plane, } } -void dpu_plane_restore(struct drm_plane *plane, struct drm_atomic_state *state) -{ - struct dpu_plane *pdpu; - - if (!plane || !plane->state) { - DPU_ERROR("invalid plane\n"); - return; - } - - pdpu = to_dpu_plane(plane); - - DPU_DEBUG_PLANE(pdpu, "\n"); - - dpu_plane_atomic_update(plane, state); -} - static void dpu_plane_destroy(struct drm_plane *plane) { struct dpu_plane *pdpu = plane ? to_dpu_plane(plane) : NULL; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h index 03b6365a750c..34e03ac05f4a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h @@ -84,12 +84,6 @@ bool is_dpu_plane_virtual(struct drm_plane *plane); void dpu_plane_get_ctl_flush(struct drm_plane *plane, struct dpu_hw_ctl *ctl, u32 *flush_sspp); -/** - * dpu_plane_restore - restore hw state if previously power collapsed - * @plane: Pointer to drm plane structure - */ -void dpu_plane_restore(struct drm_plane *plane, struct drm_atomic_state *state); - /** * dpu_plane_flush - final plane operations before commit flush * @plane: Pointer to drm plane structure -- 2.30.2

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[PATCH 1/2] mm: cma: export functions to get CMA base and size
by Lucas Stach 03 May '21

03 May '21

Make them usable in modules. Some drivers want to know where their device CMA area is located to make better decisions about the DMA programming. Signed-off-by: Lucas Stach <l.stach(a)pengutronix.de> --- mm/cma.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/mm/cma.c b/mm/cma.c index 3340ef34c154..191c89bf038d 100644 --- a/mm/cma.c +++ b/mm/cma.c @@ -44,11 +44,13 @@ phys_addr_t cma_get_base(const struct cma *cma) { return PFN_PHYS(cma->base_pfn); } +EXPORT_SYMBOL_GPL(cma_get_base); unsigned long cma_get_size(const struct cma *cma) { return cma->count << PAGE_SHIFT; } +EXPORT_SYMBOL_GPL(cma_get_size); const char *cma_get_name(const struct cma *cma) { -- 2.20.1

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dri-devel April 2021