dri-devel April 2021

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715 discussions

[PATCH] drm/amd/display: Remove duplicate include of hubp.h
by Wan Jiabing 29 Apr '21

29 Apr '21

In commit 482812d56698e ("drm/amd/display: Set max TTU on DPG enable"), "hubp.h" was added which caused the duplicate include. To be on the safe side, remove the later duplicate include. Signed-off-by: Wan Jiabing <wanjiabing(a)vivo.com> --- drivers/gpu/drm/amd/display/dc/core/dc.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 8f0a13807d05..dcaa6b1e16af 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -58,7 +58,6 @@ #include "dc_link_ddc.h" #include "dm_helpers.h" #include "mem_input.h" -#include "hubp.h" #include "dc_link_dp.h" #include "dc_dmub_srv.h" -- 2.25.1

4 5

[PATCH] [v2] drm/amd/display: Remove duplicate declaration of dc_state
by Wan Jiabing 29 Apr '21

29 Apr '21

There are two declarations of struct dc_state here. Remove the later duplicate more secure. Signed-off-by: Wan Jiabing <wanjiabing(a)vivo.com> --- Changelog: v2: - Remove the later duplicate instead of the former. --- drivers/gpu/drm/amd/display/dc/dc.h | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 8108b82bac60..6f3c95b5d1a2 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -594,7 +594,6 @@ struct dc_bounding_box_overrides { int min_dcfclk_mhz; }; -struct dc_state; struct resource_pool; struct dce_hwseq; struct gpu_info_soc_bounding_box_v1_0; -- 2.25.1

2 2

Re: [Intel-gfx] [PATCH 3/4] drm/i915: Pass ww ctx to pin_map, v2.
by Maarten Lankhorst 29 Apr '21

29 Apr '21

Op 29-04-2021 om 15:28 schreef Matthew Auld: > On Thu, 29 Apr 2021 at 11:10, Maarten Lankhorst > <maarten.lankhorst(a)linux.intel.com> wrote: >> This will allow us to explicitly pass the ww to pin_pages, >> when it starts taking it. >> >> This allows us to finally kill off the explicit passing of ww >> by retrieving it from the obj. > This seems to contradict the first sentence? Correct, this was based on a version of eviction where ww was implicitly passed. I meant 'implicit' here; the whole line can be removed. > > >> Changes since v1: >> - Rename 'ret' to ptr, fix error handling of return ptr. >> >> Signed-off-by: Maarten Lankhorst <maarten.lankhorst(a)linux.intel.com> >> --- >> .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 7 +++--- >> drivers/gpu/drm/i915/gem/i915_gem_mman.c | 2 +- >> drivers/gpu/drm/i915/gem/i915_gem_object.h | 1 + >> .../gpu/drm/i915/gem/i915_gem_object_blt.c | 4 ++-- >> drivers/gpu/drm/i915/gem/i915_gem_pages.c | 24 +++++++++++++++---- >> .../drm/i915/gem/selftests/i915_gem_context.c | 8 ++++--- >> .../drm/i915/gem/selftests/i915_gem_dmabuf.c | 2 +- >> drivers/gpu/drm/i915/gt/gen7_renderclear.c | 2 +- >> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +- >> drivers/gpu/drm/i915/gt/intel_engine_pm.c | 2 +- >> drivers/gpu/drm/i915/gt/intel_gtt.c | 2 +- >> drivers/gpu/drm/i915/gt/intel_lrc.c | 4 ++-- >> drivers/gpu/drm/i915/gt/intel_renderstate.c | 2 +- >> drivers/gpu/drm/i915/gt/intel_ring.c | 2 +- >> .../gpu/drm/i915/gt/intel_ring_submission.c | 2 +- >> drivers/gpu/drm/i915/gt/intel_timeline.c | 7 +++--- >> drivers/gpu/drm/i915/gt/intel_timeline.h | 3 ++- >> drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +- >> drivers/gpu/drm/i915/gt/mock_engine.c | 2 +- >> drivers/gpu/drm/i915/gt/selftest_lrc.c | 2 +- >> drivers/gpu/drm/i915/gt/selftest_rps.c | 10 ++++---- >> .../gpu/drm/i915/gt/selftest_workarounds.c | 6 ++--- >> drivers/gpu/drm/i915/gvt/cmd_parser.c | 4 ++-- >> drivers/gpu/drm/i915/i915_perf.c | 4 ++-- >> drivers/gpu/drm/i915/selftests/igt_spinner.c | 2 +- >> 25 files changed, 63 insertions(+), 45 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c >> index 17a87d176a67..66d24dfbd805 100644 >> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c >> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c >> @@ -1345,7 +1345,7 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb, >> if (err) >> goto err_pool; >> >> - cmd = i915_gem_object_pin_map(pool->obj, pool->type); >> + cmd = i915_gem_object_pin_map(pool->obj, &eb->ww, pool->type); >> if (IS_ERR(cmd)) { >> err = PTR_ERR(cmd); >> goto err_pool; >> @@ -2494,7 +2494,8 @@ static int eb_parse_pipeline(struct i915_execbuffer *eb, >> goto err_shadow; >> } >> >> - pw->shadow_map = i915_gem_object_pin_map(shadow->obj, I915_MAP_WB); >> + pw->shadow_map = i915_gem_object_pin_map(shadow->obj, &eb->ww, >> + I915_MAP_WB); >> if (IS_ERR(pw->shadow_map)) { >> err = PTR_ERR(pw->shadow_map); >> goto err_trampoline; >> @@ -2505,7 +2506,7 @@ static int eb_parse_pipeline(struct i915_execbuffer *eb, >> >> pw->batch_map = ERR_PTR(-ENODEV); >> if (needs_clflush && i915_has_memcpy_from_wc()) >> - pw->batch_map = i915_gem_object_pin_map(batch, I915_MAP_WC); >> + pw->batch_map = i915_gem_object_pin_map(batch, &eb->ww, I915_MAP_WC); >> >> if (IS_ERR(pw->batch_map)) { >> err = i915_gem_object_pin_pages(batch); >> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c >> index 8598a1c78a4c..ae2d71d76889 100644 >> --- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c >> +++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c >> @@ -439,7 +439,7 @@ vm_access(struct vm_area_struct *area, unsigned long addr, >> goto out; >> >> /* As this is primarily for debugging, let's focus on simplicity */ >> - vaddr = i915_gem_object_pin_map(obj, I915_MAP_FORCE_WC); >> + vaddr = i915_gem_object_pin_map(obj, &ww, I915_MAP_FORCE_WC); >> if (IS_ERR(vaddr)) { >> err = PTR_ERR(vaddr); >> goto out; >> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h b/drivers/gpu/drm/i915/gem/i915_gem_object.h >> index f7a0cf1a8f24..ed6c7421af4f 100644 >> --- a/drivers/gpu/drm/i915/gem/i915_gem_object.h >> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h >> @@ -450,6 +450,7 @@ void i915_gem_object_writeback(struct drm_i915_gem_object *obj); >> * ERR_PTR() on error. >> */ >> void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj, >> + struct i915_gem_ww_ctx *ww, >> enum i915_map_type type); >> >> void *__must_check i915_gem_object_pin_map_unlocked(struct drm_i915_gem_object *obj, >> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c >> index df8e8c18c6c9..fae18622d2da 100644 >> --- a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c >> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c >> @@ -58,7 +58,7 @@ struct i915_vma *intel_emit_vma_fill_blt(struct intel_context *ce, >> /* we pinned the pool, mark it as such */ >> intel_gt_buffer_pool_mark_used(pool); >> >> - cmd = i915_gem_object_pin_map(pool->obj, pool->type); >> + cmd = i915_gem_object_pin_map(pool->obj, ww, pool->type); >> if (IS_ERR(cmd)) { >> err = PTR_ERR(cmd); >> goto out_unpin; >> @@ -283,7 +283,7 @@ struct i915_vma *intel_emit_vma_copy_blt(struct intel_context *ce, >> /* we pinned the pool, mark it as such */ >> intel_gt_buffer_pool_mark_used(pool); >> >> - cmd = i915_gem_object_pin_map(pool->obj, pool->type); >> + cmd = i915_gem_object_pin_map(pool->obj, ww, pool->type); >> if (IS_ERR(cmd)) { >> err = PTR_ERR(cmd); >> goto out_unpin; >> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c b/drivers/gpu/drm/i915/gem/i915_gem_pages.c >> index 58e222030e10..42e867134481 100644 >> --- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c >> +++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c >> @@ -341,6 +341,7 @@ static void *i915_gem_object_map_pfn(struct drm_i915_gem_object *obj, >> >> /* get, pin, and map the pages of the object into kernel space */ >> void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj, >> + struct i915_gem_ww_ctx *ww, >> enum i915_map_type type) >> { >> enum i915_map_type has_type; >> @@ -408,13 +409,26 @@ void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj, >> void *i915_gem_object_pin_map_unlocked(struct drm_i915_gem_object *obj, >> enum i915_map_type type) >> { >> - void *ret; >> + struct i915_gem_ww_ctx ww; >> + void *ptr; >> + int err; >> >> - i915_gem_object_lock(obj, NULL); >> - ret = i915_gem_object_pin_map(obj, type); >> - i915_gem_object_unlock(obj); >> + i915_gem_ww_ctx_init(&ww, true); >> +retry: >> + err = i915_gem_object_lock(obj, &ww); >> + if (!err) { >> + ptr = i915_gem_object_pin_map(obj, &ww, type); >> + if (IS_ERR(ptr)) >> + err = PTR_ERR(ptr); >> + } >> + if (err == -EDEADLK) { >> + err = i915_gem_ww_ctx_backoff(&ww); >> + if (!err) >> + goto retry; >> + } >> + i915_gem_ww_ctx_fini(&ww); >> >> - return ret; >> + return err ? ERR_PTR(err) : ptr; >> } >> >> void __i915_gem_object_flush_map(struct drm_i915_gem_object *obj, >> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c >> index fa1ae414348b..86b3489aba33 100644 >> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c >> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c >> @@ -893,13 +893,15 @@ static int igt_shared_ctx_exec(void *arg) >> return err; >> } >> >> -static int rpcs_query_batch(struct drm_i915_gem_object *rpcs, struct i915_vma *vma) >> +static int rpcs_query_batch(struct drm_i915_gem_object *rpcs, >> + struct i915_gem_ww_ctx *ww, >> + struct i915_vma *vma) >> { >> u32 *cmd; >> >> GEM_BUG_ON(INTEL_GEN(vma->vm->i915) < 8); >> >> - cmd = i915_gem_object_pin_map(rpcs, I915_MAP_WB); >> + cmd = i915_gem_object_pin_map(rpcs, ww, I915_MAP_WB); >> if (IS_ERR(cmd)) >> return PTR_ERR(cmd); >> >> @@ -965,7 +967,7 @@ emit_rpcs_query(struct drm_i915_gem_object *obj, >> if (err) >> goto err_vma; >> >> - err = rpcs_query_batch(rpcs, vma); >> + err = rpcs_query_batch(rpcs, &ww, vma); >> if (err) >> goto err_batch; >> >> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c >> index dd74bc09ec88..3edf5a1cc0c0 100644 >> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c >> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c >> @@ -120,7 +120,7 @@ static int igt_dmabuf_import(void *arg) >> } >> >> if (0) { /* Can not yet map dmabuf */ >> - obj_map = i915_gem_object_pin_map(obj, I915_MAP_WB); >> + obj_map = i915_gem_object_pin_map(obj, NULL, I915_MAP_WB); >> if (IS_ERR(obj_map)) { >> err = PTR_ERR(obj_map); >> pr_err("i915_gem_object_pin_map failed with err=%d\n", err); >> diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c b/drivers/gpu/drm/i915/gt/gen7_renderclear.c >> index de575fdb033f..c0b0044cb52a 100644 >> --- a/drivers/gpu/drm/i915/gt/gen7_renderclear.c >> +++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c >> @@ -436,7 +436,7 @@ int gen7_setup_clear_gpr_bb(struct intel_engine_cs * const engine, >> >> GEM_BUG_ON(vma->obj->base.size < bv.size); >> >> - batch = i915_gem_object_pin_map(vma->obj, I915_MAP_WC); >> + batch = i915_gem_object_pin_map(vma->obj, NULL, I915_MAP_WC); >> if (IS_ERR(batch)) >> return PTR_ERR(batch); >> >> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c >> index 6dbdbde00f14..5a4afbbf91b2 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c >> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c >> @@ -664,7 +664,7 @@ static int init_status_page(struct intel_engine_cs *engine) >> if (ret) >> goto err; >> >> - vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB); >> + vaddr = i915_gem_object_pin_map(obj, &ww, I915_MAP_WB); >> if (IS_ERR(vaddr)) { >> ret = PTR_ERR(vaddr); >> goto err_unpin; >> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c b/drivers/gpu/drm/i915/gt/intel_engine_pm.c >> index 47f4397095e5..49add43bd4e1 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c >> +++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c >> @@ -29,7 +29,7 @@ static void dbg_poison_ce(struct intel_context *ce) >> if (!i915_gem_object_trylock(obj)) >> return; >> >> - map = i915_gem_object_pin_map(obj, type); >> + map = i915_gem_object_pin_map(obj, NULL, type); >> if (!IS_ERR(map)) { >> memset(map, CONTEXT_REDZONE, obj->base.size); >> i915_gem_object_flush_map(obj); >> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c >> index 9b98f9d9faa3..9c2d0a01c11f 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_gtt.c >> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c >> @@ -65,7 +65,7 @@ int map_pt_dma_locked(struct i915_address_space *vm, struct drm_i915_gem_object >> void *vaddr; >> >> type = i915_coherent_map_type(vm->i915, obj, true); >> - vaddr = i915_gem_object_pin_map(obj, type); >> + vaddr = i915_gem_object_pin_map(obj, NULL, type); >> if (IS_ERR(vaddr)) >> return PTR_ERR(vaddr); >> >> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c >> index aafe2a4df496..aa0e2c40e53a 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c >> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c >> @@ -902,7 +902,7 @@ lrc_pre_pin(struct intel_context *ce, >> GEM_BUG_ON(!ce->state); >> GEM_BUG_ON(!i915_vma_is_pinned(ce->state)); >> >> - *vaddr = i915_gem_object_pin_map(ce->state->obj, >> + *vaddr = i915_gem_object_pin_map(ce->state->obj, ww, >> i915_coherent_map_type(ce->engine->i915, >> ce->state->obj, >> false) | >> @@ -1514,7 +1514,7 @@ void lrc_init_wa_ctx(struct intel_engine_cs *engine) >> if (err) >> goto err; >> >> - batch = i915_gem_object_pin_map(wa_ctx->vma->obj, I915_MAP_WB); >> + batch = i915_gem_object_pin_map(wa_ctx->vma->obj, &ww, I915_MAP_WB); >> if (IS_ERR(batch)) { >> err = PTR_ERR(batch); >> goto err_unpin; >> diff --git a/drivers/gpu/drm/i915/gt/intel_renderstate.c b/drivers/gpu/drm/i915/gt/intel_renderstate.c >> index b03e197b1d99..69d4856a2b11 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_renderstate.c >> +++ b/drivers/gpu/drm/i915/gt/intel_renderstate.c >> @@ -53,7 +53,7 @@ static int render_state_setup(struct intel_renderstate *so, >> int ret = -EINVAL; >> u32 *d; >> >> - d = i915_gem_object_pin_map(so->vma->obj, I915_MAP_WB); >> + d = i915_gem_object_pin_map(so->vma->obj, &so->ww, I915_MAP_WB); >> if (IS_ERR(d)) >> return PTR_ERR(d); >> >> diff --git a/drivers/gpu/drm/i915/gt/intel_ring.c b/drivers/gpu/drm/i915/gt/intel_ring.c >> index 7c4d5158e03b..619f6d54e06d 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_ring.c >> +++ b/drivers/gpu/drm/i915/gt/intel_ring.c >> @@ -56,7 +56,7 @@ int intel_ring_pin(struct intel_ring *ring, struct i915_gem_ww_ctx *ww) >> } else { >> int type = i915_coherent_map_type(vma->vm->i915, vma->obj, false); >> >> - addr = i915_gem_object_pin_map(vma->obj, type); >> + addr = i915_gem_object_pin_map(vma->obj, ww, type); >> } >> >> if (IS_ERR(addr)) { >> diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c >> index 9585546556ee..e3903cae2d7d 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c >> +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c >> @@ -452,7 +452,7 @@ static int ring_context_init_default_state(struct intel_context *ce, >> struct drm_i915_gem_object *obj = ce->state->obj; >> void *vaddr; >> >> - vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB); >> + vaddr = i915_gem_object_pin_map(obj, ww, I915_MAP_WB); >> if (IS_ERR(vaddr)) >> return PTR_ERR(vaddr); >> >> diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c b/drivers/gpu/drm/i915/gt/intel_timeline.c >> index f19cf6d2fa85..a9a1960f7f36 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_timeline.c >> +++ b/drivers/gpu/drm/i915/gt/intel_timeline.c >> @@ -53,13 +53,14 @@ static int __timeline_active(struct i915_active *active) >> } >> >> I915_SELFTEST_EXPORT int >> -intel_timeline_pin_map(struct intel_timeline *timeline) >> +intel_timeline_pin_map(struct intel_timeline *timeline, >> + struct i915_gem_ww_ctx *ww) >> { >> struct drm_i915_gem_object *obj = timeline->hwsp_ggtt->obj; >> u32 ofs = offset_in_page(timeline->hwsp_offset); >> void *vaddr; >> >> - vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB); >> + vaddr = i915_gem_object_pin_map(obj, ww, I915_MAP_WB); >> if (IS_ERR(vaddr)) >> return PTR_ERR(vaddr); >> >> @@ -184,7 +185,7 @@ int intel_timeline_pin(struct intel_timeline *tl, struct i915_gem_ww_ctx *ww) >> return 0; >> >> if (!tl->hwsp_map) { >> - err = intel_timeline_pin_map(tl); >> + err = intel_timeline_pin_map(tl, ww); >> if (err) >> return err; >> } >> diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.h b/drivers/gpu/drm/i915/gt/intel_timeline.h >> index 57308c4d664a..dad5a60e556b 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_timeline.h >> +++ b/drivers/gpu/drm/i915/gt/intel_timeline.h >> @@ -98,6 +98,7 @@ intel_timeline_is_last(const struct intel_timeline *tl, >> return list_is_last_rcu(&rq->link, &tl->requests); >> } >> >> -I915_SELFTEST_DECLARE(int intel_timeline_pin_map(struct intel_timeline *tl)); >> +I915_SELFTEST_DECLARE(int intel_timeline_pin_map(struct intel_timeline *tl, >> + struct i915_gem_ww_ctx *ww)); >> >> #endif >> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c >> index 5a03a76bb9e2..df342b18f5ae 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c >> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c >> @@ -2233,7 +2233,7 @@ static int engine_wa_list_verify(struct intel_context *ce, >> goto err_rq; >> } >> >> - results = i915_gem_object_pin_map(vma->obj, I915_MAP_WB); >> + results = i915_gem_object_pin_map(vma->obj, NULL, I915_MAP_WB); >> if (IS_ERR(results)) { >> err = PTR_ERR(results); >> goto err_rq; >> diff --git a/drivers/gpu/drm/i915/gt/mock_engine.c b/drivers/gpu/drm/i915/gt/mock_engine.c >> index e1ba03b93ffa..b5f48e8bb38f 100644 >> --- a/drivers/gpu/drm/i915/gt/mock_engine.c >> +++ b/drivers/gpu/drm/i915/gt/mock_engine.c >> @@ -20,7 +20,7 @@ static int mock_timeline_pin(struct intel_timeline *tl) >> if (WARN_ON(!i915_gem_object_trylock(tl->hwsp_ggtt->obj))) >> return -EBUSY; >> >> - err = intel_timeline_pin_map(tl); >> + err = intel_timeline_pin_map(tl, NULL); >> i915_gem_object_unlock(tl->hwsp_ggtt->obj); >> if (err) >> return err; >> diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c >> index d8f6623524e8..84378dd775b5 100644 >> --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c >> +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c >> @@ -425,7 +425,7 @@ static int __live_lrc_state(struct intel_engine_cs *engine, >> goto err_rq; >> } >> >> - cs = i915_gem_object_pin_map(scratch->obj, I915_MAP_WB); >> + cs = i915_gem_object_pin_map(scratch->obj, NULL, I915_MAP_WB); >> if (IS_ERR(cs)) { >> err = PTR_ERR(cs); >> goto err_rq; >> diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c b/drivers/gpu/drm/i915/gt/selftest_rps.c >> index adf7fdbc00f7..687b94028de5 100644 >> --- a/drivers/gpu/drm/i915/gt/selftest_rps.c >> +++ b/drivers/gpu/drm/i915/gt/selftest_rps.c >> @@ -83,17 +83,17 @@ create_spin_counter(struct intel_engine_cs *engine, >> >> err = i915_vma_pin(vma, 0, 0, PIN_USER); >> if (err) >> - goto err_unlock; >> - >> - i915_vma_lock(vma); >> + goto err_put; >> >> - base = i915_gem_object_pin_map(obj, I915_MAP_WC); >> + base = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WC); >> if (IS_ERR(base)) { >> err = PTR_ERR(base); >> goto err_unpin; >> } >> cs = base; >> >> + i915_vma_lock(vma); >> + >> *cs++ = MI_LOAD_REGISTER_IMM(__NGPR__ * 2); >> for (i = 0; i < __NGPR__; i++) { >> *cs++ = i915_mmio_reg_offset(CS_GPR(i)); >> @@ -137,8 +137,6 @@ create_spin_counter(struct intel_engine_cs *engine, >> >> err_unpin: >> i915_vma_unpin(vma); >> -err_unlock: >> - i915_vma_unlock(vma); >> err_put: >> i915_gem_object_put(obj); >> return ERR_PTR(err); >> diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c >> index 64937ec3f2dc..1bf8e2826d7b 100644 >> --- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c >> +++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c >> @@ -223,7 +223,7 @@ static int check_whitelist(struct intel_context *ce) >> if (err) >> goto out_put; >> >> - vaddr = i915_gem_object_pin_map(results, I915_MAP_WB); >> + vaddr = i915_gem_object_pin_map(results, NULL, I915_MAP_WB); >> if (IS_ERR(vaddr)) { >> err = PTR_ERR(vaddr); >> goto out_put; >> @@ -529,13 +529,13 @@ static int check_dirty_whitelist(struct intel_context *ce) >> if (err) >> goto out; >> >> - cs = i915_gem_object_pin_map(batch->obj, I915_MAP_WC); >> + cs = i915_gem_object_pin_map(batch->obj, &ww, I915_MAP_WC); >> if (IS_ERR(cs)) { >> err = PTR_ERR(cs); >> goto out_ctx; >> } >> >> - results = i915_gem_object_pin_map(scratch->obj, I915_MAP_WB); >> + results = i915_gem_object_pin_map(scratch->obj, &ww, I915_MAP_WB); >> if (IS_ERR(results)) { >> err = PTR_ERR(results); >> goto out_unmap_batch; >> diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c >> index ca9c9e27a43d..eb804e4267d2 100644 >> --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c >> +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c >> @@ -1935,7 +1935,7 @@ static int perform_bb_shadow(struct parser_exec_state *s) >> goto err_free_bb; >> } >> >> - bb->va = i915_gem_object_pin_map(bb->obj, I915_MAP_WB); >> + bb->va = i915_gem_object_pin_map_unlocked(bb->obj, I915_MAP_WB); >> if (IS_ERR(bb->va)) { >> ret = PTR_ERR(bb->va); >> goto err_free_obj; >> @@ -3008,7 +3008,7 @@ static int shadow_indirect_ctx(struct intel_shadow_wa_ctx *wa_ctx) >> return PTR_ERR(obj); >> >> /* get the va of the shadow batch buffer */ >> - map = i915_gem_object_pin_map(obj, I915_MAP_WB); >> + map = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WB); >> if (IS_ERR(map)) { >> gvt_vgpu_err("failed to vmap shadow indirect ctx\n"); >> ret = PTR_ERR(map); >> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c >> index 85ad62dbabfa..62259c46d302 100644 >> --- a/drivers/gpu/drm/i915/i915_perf.c >> +++ b/drivers/gpu/drm/i915/i915_perf.c >> @@ -1662,7 +1662,7 @@ static int alloc_noa_wait(struct i915_perf_stream *stream) >> goto out_ww; >> } >> >> - batch = cs = i915_gem_object_pin_map(bo, I915_MAP_WB); >> + batch = cs = i915_gem_object_pin_map(bo, &ww, I915_MAP_WB); >> if (IS_ERR(batch)) { >> ret = PTR_ERR(batch); >> goto err_unpin; >> @@ -1875,7 +1875,7 @@ alloc_oa_config_buffer(struct i915_perf_stream *stream, >> if (err) >> goto out_ww; >> >> - cs = i915_gem_object_pin_map(obj, I915_MAP_WB); >> + cs = i915_gem_object_pin_map(obj, &ww, I915_MAP_WB); >> if (IS_ERR(cs)) { >> err = PTR_ERR(cs); >> goto out_ww; >> diff --git a/drivers/gpu/drm/i915/selftests/igt_spinner.c b/drivers/gpu/drm/i915/selftests/igt_spinner.c >> index 5fe397b7d1d9..b80d0089923a 100644 >> --- a/drivers/gpu/drm/i915/selftests/igt_spinner.c >> +++ b/drivers/gpu/drm/i915/selftests/igt_spinner.c >> @@ -54,7 +54,7 @@ static void *igt_spinner_pin_obj(struct intel_context *ce, >> if (ret) >> return ERR_PTR(ret); >> >> - vaddr = i915_gem_object_pin_map(obj, mode); >> + vaddr = i915_gem_object_pin_map(obj, ww, mode); >> >> if (!ww) >> i915_gem_object_unlock(obj); >> -- >> 2.31.0 >> >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx(a)lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

1 0

[Bug 212881] New: nouveau: BUG: kernel NULL pointer dereference in nouveau_bo_sync_for_device
by bugzilla-daemon＠bugzilla.kernel.org 29 Apr '21

29 Apr '21

https://bugzilla.kernel.org/show_bug.cgi?id=212881 Bug ID: 212881 Summary: nouveau: BUG: kernel NULL pointer dereference in nouveau_bo_sync_for_device Product: Drivers Version: 2.5 Kernel Version: 5.11.0 Hardware: Intel OS: Linux Tree: Mainline Status: NEW Severity: normal Priority: P1 Component: Video(DRI - non Intel) Assignee: drivers_video-dri(a)kernel-bugs.osdl.org Reporter: dave.mueller(a)gmx.ch Regression: No Since kernel 5.11, the nouveau driver crash with a NULL pointer exception. Below is the (stripped) dmesg output from kernel 5.12, which still shows the same problem. The same (old) hardware works fine with kernel 5.10. [ 0.000000] Linux version 5.12.0 (root@test) (gcc (GCC) 5.5.0, GNU ld version 2.27-slack15) #2 PREEMPT Wed Apr 28 15:34:45 CEST 2021 [ 11.415023] nouveau 0000:01:00.0: vgaarb: deactivate vga console [ 11.416766] Console: switching to colour dummy device 80x25 [ 11.417616] nouveau 0000:01:00.0: NVIDIA NV17 (017200a5) [ 11.517414] nouveau 0000:01:00.0: bios: version 04.17.00.45.00 [ 11.518545] agpgart-intel 0000:00:00.0: AGP 2.0 bridge [ 11.518692] agpgart-intel 0000:00:00.0: putting AGP V2 device into 4x mode [ 11.518748] nouveau 0000:01:00.0: putting AGP V2 device into 4x mode [ 11.518918] agpgart-intel 0000:00:00.0: AGP 2.0 bridge [ 11.518941] agpgart-intel 0000:00:00.0: putting AGP V2 device into 4x mode [ 11.518977] nouveau 0000:01:00.0: putting AGP V2 device into 4x mode [ 11.519038] nouveau 0000:01:00.0: timer: unknown input clock freq [ 11.521866] nouveau 0000:01:00.0: fb: 64 MiB DDR1 [ 11.522352] sr 2:0:0:0: Attached scsi CD-ROM sr1 [ 11.534498] [TTM] Zone kernel: Available graphics memory: 569334 KiB [ 11.534524] [TTM] Zone highmem: Available graphics memory: 1033956 KiB [ 11.534581] nouveau 0000:01:00.0: DRM: VRAM: 63 MiB [ 11.534593] nouveau 0000:01:00.0: DRM: GART: 128 MiB [ 11.534604] nouveau 0000:01:00.0: DRM: BMP version 5.21 [ 11.534614] nouveau 0000:01:00.0: DRM: DCB version 2.0 [ 11.534625] nouveau 0000:01:00.0: DRM: DCB outp 00: 01000100 000088b8 [ 11.534636] nouveau 0000:01:00.0: DRM: DCB outp 01: 02010111 00000003 [ 11.534646] nouveau 0000:01:00.0: DRM: DCB outp 02: 02010211 00000003 [ 11.534657] nouveau 0000:01:00.0: DRM: Merging DCB entries 1 and 2 [ 11.535551] nouveau 0000:01:00.0: DRM: Loading NV17 power sequencing microcode [ 11.536036] BUG: kernel NULL pointer dereference, address: 00000000 [ 11.536053] #PF: supervisor read access in kernel mode [ 11.536062] #PF: error_code(0x0000) - not-present page [ 11.536070] *pde = 00000000 [ 11.536079] Oops: 0000 [#1] PREEMPT [ 11.536089] CPU: 0 PID: 388 Comm: udevd Not tainted 5.12.0 #2 [ 11.536099] Hardware name: Dell Computer Corporation Dimension 4550 /, BIOS A08 09/23/2003 [ 11.536110] EIP: nouveau_bo_sync_for_device+0x91/0x103 [nouveau] [ 11.536393] Code: 85 8b 00 00 00 bb 01 00 00 00 eb 08 83 c2 24 3b 14 87 75 0a 83 c3 01 83 c0 01 39 c1 77 ee 89 d9 c1 e1 0c 8b 45 10 8b 7c 24 10 <8b> 14 38 8b 44 24 14 8b 40 e0 8b 40 08 c7 04 24 01 00 00 00 e8 7b [ 11.536411] EAX: 00000000 EBX: 00000010 ECX: 00010000 EDX: f624e040 [ 11.536421] ESI: 00000000 EDI: 00000000 EBP: b20f5cc0 ESP: b1c83b44 [ 11.536430] DS: 007b ES: 007b FS: 0000 GS: 00e0 SS: 0068 EFLAGS: 00010206 [ 11.536439] CR0: 80050033 CR2: 00000000 CR3: 01c63000 CR4: 000006d0 [ 11.536449] Call Trace: [ 11.536459] ? nouveau_bo_validate+0x5d/0x77 [nouveau] [ 11.536780] ? nouveau_bo_pin+0x10e/0x287 [nouveau] [ 11.537099] ? nouveau_bo_new+0x64/0x74 [nouveau] [ 11.537418] ? nouveau_channel_prep+0x113/0x32e [nouveau] [ 11.537744] ? nouveau_channel_new+0x59/0x75d [nouveau] [ 11.538067] ? ttm_bo_kmap+0x1a7/0x1f0 [ttm] [ 11.538084] ? ttm_bo_kmap+0x1a7/0x1f0 [ttm] [ 11.538098] ? nouveau_bo_pin+0x150/0x287 [nouveau] [ 11.538417] ? nouveau_bo_map+0x75/0x8b [nouveau] [ 11.538736] ? nvif_object_sclass_put+0xa/0x12 [nouveau] [ 11.538976] ? kfree+0x66/0xca [ 11.538992] ? nouveau_drm_device_init+0x42f/0x7d7 [nouveau] [ 11.539311] ? pci_read_config_word+0x27/0x2c [ 11.539325] ? pci_enable_device_flags+0xd0/0xe5 [ 11.539335] ? nouveau_drm_probe+0x110/0x1e5 [nouveau] [ 11.539654] ? nouveau_drm_device_init+0x7d7/0x7d7 [nouveau] [ 11.539973] ? pci_device_probe+0x82/0xf0 [ 11.539984] ? sysfs_create_link+0x1d/0x2e [ 11.539996] ? really_probe+0x19a/0x341 [ 11.540007] ? driver_probe_device+0x3d/0x85 [ 11.540016] ? device_driver_attach+0x3c/0x40 [ 11.540024] ? __driver_attach+0x6f/0x95 [ 11.540033] ? device_driver_attach+0x40/0x40 [ 11.540041] ? bus_for_each_dev+0x48/0x88 [ 11.540049] ? driver_attach+0x16/0x1a [ 11.540056] ? device_driver_attach+0x40/0x40 [ 11.540065] ? bus_add_driver+0x111/0x1b4 [ 11.540073] ? driver_register+0x51/0xe5 [ 11.540083] ? nouveau_drm_init+0x12c/0x1000 [nouveau] [ 11.540281] ? 0xf7fba000 [ 11.540288] ? do_one_initcall+0x41/0x1a6 [ 11.540300] ? do_init_module+0x42/0x1c7 [ 11.540311] ? load_module+0x2040/0x24cb [ 11.540327] ? __ia32_sys_init_module+0x129/0x14d [ 11.540338] ? do_int80_syscall_32+0x29/0x34 [ 11.540349] ? entry_INT80_32+0xf3/0xf3 [ 11.540362] Modules linked in: nouveau(+) btusb btrtl btbcm btintel bluetooth ftdi_sio usbserial ecdh_generic ecc rfkill mousedev usb_storage hwmon wmi video i2c_algo_bit drm_ttm_helper ttm drm_kms_helper i2c_dev evdev cfbfillrect input_leds syscopyarea psmouse cfbimgblt led_class sysfillrect sysimgblt dcdbas fb_sys_fops serio_raw sr_mod i2c_i801 cdrom cfbcopyarea i2c_smbus snd_emu10k1x drm snd_ac97_codec ac97_bus snd_rawmidi snd_seq_device e100 ohci_pci firewire_ohci snd_pcm ohci_hcd mii firewire_core crc_itu_t snd_timer uhci_hcd snd ehci_pci i2c_core ehci_hcd drm_panel_orientation_quirks soundcore backlight usbcore parport_pc 8250 floppy parport 8250_base rtc_cmos lpc_ich mfd_core intel_agp serial_core intel_gtt tiny_power_button agpgart intel_rng usb_common button rng_core processor loop [ 11.540544] CR2: 0000000000000000 [ 11.540642] ---[ end trace 1cf246b74e8c5b23 ]--- [ 11.540654] EIP: nouveau_bo_sync_for_device+0x91/0x103 [nouveau] [ 11.540898] Code: 85 8b 00 00 00 bb 01 00 00 00 eb 08 83 c2 24 3b 14 87 75 0a 83 c3 01 83 c0 01 39 c1 77 ee 89 d9 c1 e1 0c 8b 45 10 8b 7c 24 10 <8b> 14 38 8b 44 24 14 8b 40 e0 8b 40 08 c7 04 24 01 00 00 00 e8 7b [ 11.540915] EAX: 00000000 EBX: 00000010 ECX: 00010000 EDX: f624e040 [ 11.540925] ESI: 00000000 EDI: 00000000 EBP: b20f5cc0 ESP: b1c83b44 [ 11.540934] DS: 007b ES: 007b FS: 0000 GS: 00e0 SS: 0068 EFLAGS: 00010206 [ 11.540943] CR0: 80050033 CR2: 00000000 CR3: 01c63000 CR4: 000006d0 -- You may reply to this email to add a comment. You are receiving this mail because: You are watching the assignee of the bug.

1 1

[PATCH] drm/amd/display: Remove duplicate declaration of dc_state
by Wan Jiabing 29 Apr '21

29 Apr '21

There are two declarations of struct dc_state here. The later one is closer to its user. Remove the former duplicate. Signed-off-by: Wan Jiabing <wanjiabing(a)vivo.com> --- drivers/gpu/drm/amd/display/dc/dc.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 8108b82bac60..cad045db6ea2 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -276,8 +276,6 @@ enum surface_update_type { /* Forward declaration*/ struct dc; struct dc_plane_state; -struct dc_state; - struct dc_cap_funcs { bool (*get_dcc_compression_cap)(const struct dc *dc, -- 2.25.1

3 2

Re: [PATCH 1/1] i915/query: Correlate engine and cpu timestamps with better accuracy
by Jani Nikula 29 Apr '21

29 Apr '21

On Tue, 27 Apr 2021, Umesh Nerlige Ramappa <umesh.nerlige.ramappa(a)intel.com> wrote: > Perf measurements rely on CPU and engine timestamps to correlate > events of interest across these time domains. Current mechanisms get > these timestamps separately and the calculated delta between these > timestamps lack enough accuracy. > > To improve the accuracy of these time measurements to within a few us, > add a query that returns the engine and cpu timestamps captured as > close to each other as possible. Cc: dri-devel, Jason and Daniel for review. > > v2: (Tvrtko) > - document clock reference used > - return cpu timestamp always > - capture cpu time just before lower dword of cs timestamp > > v3: (Chris) > - use uncore-rpm > - use __query_cs_timestamp helper > > v4: (Lionel) > - Kernel perf subsytem allows users to specify the clock id to be used > in perf_event_open. This clock id is used by the perf subsystem to > return the appropriate cpu timestamp in perf events. Similarly, let > the user pass the clockid to this query so that cpu timestamp > corresponds to the clock id requested. > > v5: (Tvrtko) > - Use normal ktime accessors instead of fast versions > - Add more uApi documentation > > v6: (Lionel) > - Move switch out of spinlock > > v7: (Chris) > - cs_timestamp is a misnomer, use cs_cycles instead > - return the cs cycle frequency as well in the query > > v8: > - Add platform and engine specific checks > > v9: (Lionel) > - Return 2 cpu timestamps in the query - captured before and after the > register read > > v10: (Chris) > - Use local_clock() to measure time taken to read lower dword of > register and return it to user. > > v11: (Jani) > - IS_GEN deprecated. User GRAPHICS_VER instead. > > Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa(a)intel.com> > --- > drivers/gpu/drm/i915/i915_query.c | 145 ++++++++++++++++++++++++++++++ > include/uapi/drm/i915_drm.h | 48 ++++++++++ > 2 files changed, 193 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c > index fed337ad7b68..2594b93901ac 100644 > --- a/drivers/gpu/drm/i915/i915_query.c > +++ b/drivers/gpu/drm/i915/i915_query.c > @@ -6,6 +6,8 @@ > > #include <linux/nospec.h> > > +#include "gt/intel_engine_pm.h" > +#include "gt/intel_engine_user.h" > #include "i915_drv.h" > #include "i915_perf.h" > #include "i915_query.h" > @@ -90,6 +92,148 @@ static int query_topology_info(struct drm_i915_private *dev_priv, > return total_length; > } > > +typedef u64 (*__ktime_func_t)(void); > +static __ktime_func_t __clock_id_to_func(clockid_t clk_id) > +{ > + /* > + * Use logic same as the perf subsystem to allow user to select the > + * reference clock id to be used for timestamps. > + */ > + switch (clk_id) { > + case CLOCK_MONOTONIC: > + return &ktime_get_ns; > + case CLOCK_MONOTONIC_RAW: > + return &ktime_get_raw_ns; > + case CLOCK_REALTIME: > + return &ktime_get_real_ns; > + case CLOCK_BOOTTIME: > + return &ktime_get_boottime_ns; > + case CLOCK_TAI: > + return &ktime_get_clocktai_ns; > + default: > + return NULL; > + } > +} > + > +static inline int > +__read_timestamps(struct intel_uncore *uncore, > + i915_reg_t lower_reg, > + i915_reg_t upper_reg, > + u64 *cs_ts, > + u64 *cpu_ts, > + __ktime_func_t cpu_clock) > +{ > + u32 upper, lower, old_upper, loop = 0; > + > + upper = intel_uncore_read_fw(uncore, upper_reg); > + do { > + cpu_ts[1] = local_clock(); > + cpu_ts[0] = cpu_clock(); > + lower = intel_uncore_read_fw(uncore, lower_reg); > + cpu_ts[1] = local_clock() - cpu_ts[1]; > + old_upper = upper; > + upper = intel_uncore_read_fw(uncore, upper_reg); > + } while (upper != old_upper && loop++ < 2); > + > + *cs_ts = (u64)upper << 32 | lower; > + > + return 0; > +} > + > +static int > +__query_cs_cycles(struct intel_engine_cs *engine, > + u64 *cs_ts, u64 *cpu_ts, > + __ktime_func_t cpu_clock) > +{ > + struct intel_uncore *uncore = engine->uncore; > + enum forcewake_domains fw_domains; > + u32 base = engine->mmio_base; > + intel_wakeref_t wakeref; > + int ret; > + > + fw_domains = intel_uncore_forcewake_for_reg(uncore, > + RING_TIMESTAMP(base), > + FW_REG_READ); > + > + with_intel_runtime_pm(uncore->rpm, wakeref) { > + spin_lock_irq(&uncore->lock); > + intel_uncore_forcewake_get__locked(uncore, fw_domains); > + > + ret = __read_timestamps(uncore, > + RING_TIMESTAMP(base), > + RING_TIMESTAMP_UDW(base), > + cs_ts, > + cpu_ts, > + cpu_clock); > + > + intel_uncore_forcewake_put__locked(uncore, fw_domains); > + spin_unlock_irq(&uncore->lock); > + } > + > + return ret; > +} > + > +static int > +query_cs_cycles(struct drm_i915_private *i915, > + struct drm_i915_query_item *query_item) > +{ > + struct drm_i915_query_cs_cycles __user *query_ptr; > + struct drm_i915_query_cs_cycles query; > + struct intel_engine_cs *engine; > + __ktime_func_t cpu_clock; > + int ret; > + > + if (GRAPHICS_VER(i915) < 6) > + return -ENODEV; > + > + query_ptr = u64_to_user_ptr(query_item->data_ptr); > + ret = copy_query_item(&query, sizeof(query), sizeof(query), query_item); > + if (ret != 0) > + return ret; > + > + if (query.flags) > + return -EINVAL; > + > + if (query.rsvd) > + return -EINVAL; > + > + cpu_clock = __clock_id_to_func(query.clockid); > + if (!cpu_clock) > + return -EINVAL; > + > + engine = intel_engine_lookup_user(i915, > + query.engine.engine_class, > + query.engine.engine_instance); > + if (!engine) > + return -EINVAL; > + > + if (GRAPHICS_VER(i915) == 6 && > + query.engine.engine_class != I915_ENGINE_CLASS_RENDER) > + return -ENODEV; > + > + query.cs_frequency = engine->gt->clock_frequency; > + ret = __query_cs_cycles(engine, > + &query.cs_cycles, > + query.cpu_timestamp, > + cpu_clock); > + if (ret) > + return ret; > + > + if (put_user(query.cs_frequency, &query_ptr->cs_frequency)) > + return -EFAULT; > + > + if (put_user(query.cpu_timestamp[0], &query_ptr->cpu_timestamp[0])) > + return -EFAULT; > + > + if (put_user(query.cpu_timestamp[1], &query_ptr->cpu_timestamp[1])) > + return -EFAULT; > + > + if (put_user(query.cs_cycles, &query_ptr->cs_cycles)) > + return -EFAULT; > + > + return sizeof(query); > +} > + > static int > query_engine_info(struct drm_i915_private *i915, > struct drm_i915_query_item *query_item) > @@ -424,6 +568,7 @@ static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv, > query_topology_info, > query_engine_info, > query_perf_config, > + query_cs_cycles, > }; > > int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file) > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h > index 6a34243a7646..08b00f1709b5 100644 > --- a/include/uapi/drm/i915_drm.h > +++ b/include/uapi/drm/i915_drm.h > @@ -2230,6 +2230,10 @@ struct drm_i915_query_item { > #define DRM_I915_QUERY_TOPOLOGY_INFO 1 > #define DRM_I915_QUERY_ENGINE_INFO 2 > #define DRM_I915_QUERY_PERF_CONFIG 3 > + /** > + * Query Command Streamer timestamp register. > + */ > +#define DRM_I915_QUERY_CS_CYCLES 4 > /* Must be kept compact -- no holes and well documented */ > > /** > @@ -2397,6 +2401,50 @@ struct drm_i915_engine_info { > __u64 rsvd1[4]; > }; > > +/** > + * struct drm_i915_query_cs_cycles > + * > + * The query returns the command streamer cycles and the frequency that can be > + * used to calculate the command streamer timestamp. In addition the query > + * returns a set of cpu timestamps that indicate when the command streamer cycle > + * count was captured. > + */ > +struct drm_i915_query_cs_cycles { > + /** Engine for which command streamer cycles is queried. */ > + struct i915_engine_class_instance engine; > + > + /** Must be zero. */ > + __u32 flags; > + > + /** > + * Command streamer cycles as read from the command streamer > + * register at 0x358 offset. > + */ > + __u64 cs_cycles; > + > + /** Frequency of the cs cycles in Hz. */ > + __u64 cs_frequency; > + > + /** > + * CPU timestamps in ns. cpu_timestamp[0] is captured before reading the > + * cs_cycles register using the reference clockid set by the user. > + * cpu_timestamp[1] is the time taken in ns to read the lower dword of > + * the cs_cycles register. > + */ > + __u64 cpu_timestamp[2]; > + > + /** > + * Reference clock id for CPU timestamp. For definition, see > + * clock_gettime(2) and perf_event_open(2). Supported clock ids are > + * CLOCK_MONOTONIC, CLOCK_MONOTONIC_RAW, CLOCK_REALTIME, CLOCK_BOOTTIME, > + * CLOCK_TAI. > + */ > + __s32 clockid; > + > + /** Must be zero. */ > + __u32 rsvd; > +}; > + > /** > * struct drm_i915_query_engine_info > * -- Jani Nikula, Intel Open Source Graphics Center

4 8

[PATCH v2 1/9] drm/doc/rfc: i915 DG1 uAPI
by Matthew Auld 29 Apr '21

29 Apr '21

Add an entry for the new uAPI needed for DG1. Also add the overall upstream plan, including some notes for the TTM conversion. v2(Daniel): - include the overall upstreaming plan - add a note for mmap, there are differences here for TTM vs i915 - bunch of other suggestions from Daniel v3: (Daniel) - add a note for set/get caching stuff - add some more docs for existing query and extensions stuff - add an actual code example for regions query - bunch of other stuff (Jason) - uAPI change(!): - try a simpler design with the placements extension - rather than have a generic setparam which can cover multiple use cases, have each extension be responsible for one thing only v4: (Daniel) - add some more notes for ttm conversion - bunch of other stuff (Jason) - uAPI change(!): - drop all the extra rsvd members for the region_query and region_info, just keep the bare minimum needed for padding v5: (Jason) - for the upstream plan, add a requirement that we send the uAPI bits again for final sign off before turning it on for real - document how we intend to extend the rsvd bits for the region query (Kenneth) - improve the comment for the smem+lmem mmap mode and caching Signed-off-by: Matthew Auld <matthew.auld(a)intel.com> Cc: Joonas Lahtinen <joonas.lahtinen(a)linux.intel.com> Cc: Thomas Hellström <thomas.hellstrom(a)linux.intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio(a)intel.com> Cc: Lionel Landwerlin <lionel.g.landwerlin(a)linux.intel.com> Cc: Jon Bloomfield <jon.bloomfield(a)intel.com> Cc: Jordan Justen <jordan.l.justen(a)intel.com> Cc: Daniel Vetter <daniel.vetter(a)intel.com> Cc: Kenneth Graunke <kenneth(a)whitecape.org> Cc: Jason Ekstrand <jason(a)jlekstrand.net> Cc: Dave Airlie <airlied(a)gmail.com> Cc: dri-devel(a)lists.freedesktop.org Cc: mesa-dev(a)lists.freedesktop.org Acked-by: Daniel Vetter <daniel.vetter(a)ffwll.ch> Acked-by: Dave Airlie <airlied(a)redhat.com> Acked-by: Kenneth Graunke <kenneth(a)whitecape.org> Acked-by: Jon Bloomfield <jon.bloomfield(a)intel.com> --- Documentation/gpu/rfc/i915_gem_lmem.h | 237 ++++++++++++++++++++++++ Documentation/gpu/rfc/i915_gem_lmem.rst | 131 +++++++++++++ Documentation/gpu/rfc/index.rst | 4 + 3 files changed, 372 insertions(+) create mode 100644 Documentation/gpu/rfc/i915_gem_lmem.h create mode 100644 Documentation/gpu/rfc/i915_gem_lmem.rst diff --git a/Documentation/gpu/rfc/i915_gem_lmem.h b/Documentation/gpu/rfc/i915_gem_lmem.h new file mode 100644 index 000000000000..712a85f932ec --- /dev/null +++ b/Documentation/gpu/rfc/i915_gem_lmem.h @@ -0,0 +1,237 @@ +/** + * enum drm_i915_gem_memory_class - Supported memory classes + */ +enum drm_i915_gem_memory_class { + /** @I915_MEMORY_CLASS_SYSTEM: System memory */ + I915_MEMORY_CLASS_SYSTEM = 0, + /** @I915_MEMORY_CLASS_DEVICE: Device local-memory */ + I915_MEMORY_CLASS_DEVICE, +}; + +/** + * struct drm_i915_gem_memory_class_instance - Identify particular memory region + */ +struct drm_i915_gem_memory_class_instance { + /** @memory_class: See enum drm_i915_gem_memory_class */ + __u16 memory_class; + + /** @memory_instance: Which instance */ + __u16 memory_instance; +}; + +/** + * struct drm_i915_memory_region_info - Describes one region as known to the + * driver. + * + * Note that we reserve some stuff here for potential future work. As an example + * we might want expose the capabilities for a given region, which could include + * things like if the region is CPU mappable/accessible, what are the supported + * mapping types etc. + * + * Note that to extend struct drm_i915_memory_region_info and struct + * drm_i915_query_memory_regions in the future the plan is to do the following: + * + * .. code-block:: C + * + * struct drm_i915_memory_region_info { + * struct drm_i915_gem_memory_class_instance region; + * union { + * __u32 rsvd0; + * __u32 new_thing1; + * }; + * ... + * union { + * __u64 rsvd1[8]; + * struct { + * __u64 new_thing2; + * __u64 new_thing3; + * ... + * }; + * }; + * }; + * + * With this things should remain source compatible between versions for + * userspace, even as we add new fields. + * + * Note this is using both struct drm_i915_query_item and struct drm_i915_query. + * For this new query we are adding the new query id DRM_I915_QUERY_MEMORY_REGIONS + * at &drm_i915_query_item.query_id. + */ +struct drm_i915_memory_region_info { + /** @region: The class:instance pair encoding */ + struct drm_i915_gem_memory_class_instance region; + + /** @rsvd0: MBZ */ + __u32 rsvd0; + + /** @probed_size: Memory probed by the driver (-1 = unknown) */ + __u64 probed_size; + + /** @unallocated_size: Estimate of memory remaining (-1 = unknown) */ + __u64 unallocated_size; + + /** @rsvd1: MBZ */ + __u64 rsvd1[8]; +}; + +/** + * struct drm_i915_query_memory_regions + * + * The region info query enumerates all regions known to the driver by filling + * in an array of struct drm_i915_memory_region_info structures. + * + * Example for getting the list of supported regions: + * + * .. code-block:: C + * + * struct drm_i915_query_memory_regions *info; + * struct drm_i915_query_item item = { + * .query_id = DRM_I915_QUERY_MEMORY_REGIONS; + * }; + * struct drm_i915_query query = { + * .num_items = 1, + * .items_ptr = (uintptr_t)&item, + * }; + * int err, i; + * + * // First query the size of the blob we need, this needs to be large + * // enough to hold our array of regions. The kernel will fill out the + * // item.length for us, which is the number of bytes we need. + * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); + * if (err) ... + * + * info = calloc(1, item.length); + * // Now that we allocated the required number of bytes, we call the ioctl + * // again, this time with the data_ptr pointing to our newly allocated + * // blob, which the kernel can then populate with the all the region info. + * item.data_ptr = (uintptr_t)&info, + * + * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); + * if (err) ... + * + * // We can now access each region in the array + * for (i = 0; i < info->num_regions; i++) { + * struct drm_i915_memory_region_info mr = info->regions[i]; + * u16 class = mr.region.class; + * u16 instance = mr.region.instance; + * + * .... + * } + * + * free(info); + */ +struct drm_i915_query_memory_regions { + /** @num_regions: Number of supported regions */ + __u32 num_regions; + + /** @rsvd: MBZ */ + __u32 rsvd[3]; + + /** @regions: Info about each supported region */ + struct drm_i915_memory_region_info regions[]; +}; + +#define DRM_I915_GEM_CREATE_EXT 0xdeadbeaf +#define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE_EXT, struct drm_i915_gem_create_ext) + +/** + * struct drm_i915_gem_create_ext - Existing gem_create behaviour, with added + * extension support using struct i915_user_extension. + * + * Note that in the future we want to have our buffer flags here, at least for + * the stuff that is immutable. Previously we would have two ioctls, one to + * create the object with gem_create, and another to apply various parameters, + * however this creates some ambiguity for the params which are considered + * immutable. Also in general we're phasing out the various SET/GET ioctls. + */ +struct drm_i915_gem_create_ext { + /** + * @size: Requested size for the object. + * + * The (page-aligned) allocated size for the object will be returned. + * + * Note that for some devices we have might have further minimum + * page-size restrictions(larger than 4K), like for device local-memory. + * However in general the final size here should always reflect any + * rounding up, if for example using the I915_GEM_CREATE_EXT_MEMORY_REGIONS + * extension to place the object in device local-memory. + */ + __u64 size; + /** + * @handle: Returned handle for the object. + * + * Object handles are nonzero. + */ + __u32 handle; + /** @flags: MBZ */ + __u32 flags; + /** + * @extensions: The chain of extensions to apply to this object. + * + * This will be useful in the future when we need to support several + * different extensions, and we need to apply more than one when + * creating the object. See struct i915_user_extension. + * + * If we don't supply any extensions then we get the same old gem_create + * behaviour. + * + * For I915_GEM_CREATE_EXT_MEMORY_REGIONS usage see + * struct drm_i915_gem_create_ext_memory_regions. + */ +#define I915_GEM_CREATE_EXT_MEMORY_REGIONS 0 + __u64 extensions; +}; + +/** + * struct drm_i915_gem_create_ext_memory_regions - The + * I915_GEM_CREATE_EXT_MEMORY_REGIONS extension. + * + * Set the object with the desired set of placements/regions in priority + * order. Each entry must be unique and supported by the device. + * + * This is provided as an array of struct drm_i915_gem_memory_class_instance, or + * an equivalent layout of class:instance pair encodings. See struct + * drm_i915_query_memory_regions and DRM_I915_QUERY_MEMORY_REGIONS for how to + * query the supported regions for a device. + * + * As an example, on discrete devices, if we wish to set the placement as + * device local-memory we can do something like: + * + * .. code-block:: C + * + * struct drm_i915_gem_memory_class_instance region_lmem = { + * .memory_class = I915_MEMORY_CLASS_DEVICE, + * .memory_instance = 0, + * }; + * struct drm_i915_gem_create_ext_memory_regions regions = { + * .base = { .name = I915_GEM_CREATE_EXT_MEMORY_REGIONS }, + * .regions = (uintptr_t)&region_lmem, + * .num_regions = 1, + * }; + * struct drm_i915_gem_create_ext create_ext = { + * .size = 16 * PAGE_SIZE, + * .extensions = (uintptr_t)&regions, + * }; + * + * int err = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext); + * if (err) ... + * + * At which point we get the object handle in &drm_i915_gem_create_ext.handle, + * along with the final object size in &drm_i915_gem_create_ext.size, which + * should account for any rounding up, if required. + */ +struct drm_i915_gem_create_ext_memory_regions { + /** @base: Extension link. See struct i915_user_extension. */ + struct i915_user_extension base; + + /** @pad: MBZ */ + __u32 pad; + /** @num_regions: Number of elements in the @regions array. */ + __u32 num_regions; + /** + * @regions: The regions/placements array. + * + * An array of struct drm_i915_gem_memory_class_instance. + */ + __u64 regions; +}; diff --git a/Documentation/gpu/rfc/i915_gem_lmem.rst b/Documentation/gpu/rfc/i915_gem_lmem.rst new file mode 100644 index 000000000000..1d344c593018 --- /dev/null +++ b/Documentation/gpu/rfc/i915_gem_lmem.rst @@ -0,0 +1,131 @@ +========================= +I915 DG1/LMEM RFC Section +========================= + +Upstream plan +============= +For upstream the overall plan for landing all the DG1 stuff and turning it for +real, with all the uAPI bits is: + +* Merge basic HW enabling of DG1(still without pciid) +* Merge the uAPI bits behind special CONFIG_BROKEN(or so) flag + * At this point we can still make changes, but importantly this lets us + start running IGTs which can utilize local-memory in CI +* Convert over to TTM, make sure it all keeps working. Some of the work items: + * TTM shrinker for discrete + * dma_resv_lockitem for full dma_resv_lock, i.e not just trylock + * Use TTM CPU pagefault handler + * Route shmem backend over to TTM SYSTEM for discrete + * TTM purgeable object support + * Move i915 buddy allocator over to TTM + * MMAP ioctl mode(see `I915 MMAP`_) + * SET/GET ioctl caching(see `I915 SET/GET CACHING`_) +* Send RFC(with mesa-dev on cc) for final sign off on the uAPI +* Add pciid for DG1 and turn on uAPI for real + +New object placement and region query uAPI +========================================== +Starting from DG1 we need to give userspace the ability to allocate buffers from +device local-memory. Currently the driver supports gem_create, which can place +buffers in system memory via shmem, and the usual assortment of other +interfaces, like dumb buffers and userptr. + +To support this new capability, while also providing a uAPI which will work +beyond just DG1, we propose to offer three new bits of uAPI: + +DRM_I915_QUERY_MEMORY_REGIONS +----------------------------- +New query ID which allows userspace to discover the list of supported memory +regions(like system-memory and local-memory) for a given device. We identify +each region with a class and instance pair, which should be unique. The class +here would be DEVICE or SYSTEM, and the instance would be zero, on platforms +like DG1. + +Side note: The class/instance design is borrowed from our existing engine uAPI, +where we describe every physical engine in terms of its class, and the +particular instance, since we can have more than one per class. + +In the future we also want to expose more information which can further +describe the capabilities of a region. + +.. kernel-doc:: Documentation/gpu/rfc/i915_gem_lmem.h + :functions: drm_i915_gem_memory_class drm_i915_gem_memory_class_instance drm_i915_memory_region_info drm_i915_query_memory_regions + +GEM_CREATE_EXT +-------------- +New ioctl which is basically just gem_create but now allows userspace to provide +a chain of possible extensions. Note that if we don't provide any extensions and +set flags=0 then we get the exact same behaviour as gem_create. + +Side note: We also need to support PXP[1] in the near future, which is also +applicable to integrated platforms, and adds its own gem_create_ext extension, +which basically lets userspace mark a buffer as "protected". + +.. kernel-doc:: Documentation/gpu/rfc/i915_gem_lmem.h + :functions: drm_i915_gem_create_ext + +I915_GEM_CREATE_EXT_MEMORY_REGIONS +---------------------------------- +Implemented as an extension for gem_create_ext, we would now allow userspace to +optionally provide an immutable list of preferred placements at creation time, +in priority order, for a given buffer object. For the placements we expect +them each to use the class/instance encoding, as per the output of the regions +query. Having the list in priority order will be useful in the future when +placing an object, say during eviction. + +.. kernel-doc:: Documentation/gpu/rfc/i915_gem_lmem.h + :functions: drm_i915_gem_create_ext_memory_regions + +One fair criticism here is that this seems a little over-engineered[2]. If we +just consider DG1 then yes, a simple gem_create.flags or something is totally +all that's needed to tell the kernel to allocate the buffer in local-memory or +whatever. However looking to the future we need uAPI which can also support +upcoming Xe HP multi-tile architecture in a sane way, where there can be +multiple local-memory instances for a given device, and so using both class and +instance in our uAPI to describe regions is desirable, although specifically +for DG1 it's uninteresting, since we only have a single local-memory instance. + +Existing uAPI issues +==================== +Some potential issues we still need to resolve. + +I915 MMAP +--------- +In i915 there are multiple ways to MMAP GEM object, including mapping the same +object using different mapping types(WC vs WB), i.e multiple active mmaps per +object. TTM expects one MMAP at most for the lifetime of the object. If it +turns out that we have to backpedal here, there might be some potential +userspace fallout. + +I915 SET/GET CACHING +-------------------- +In i915 we have set/get_caching ioctl. TTM doesn't let us to change this, but +DG1 doesn't support non-snooped pcie transactions, so we can just always +allocate as WB for smem-only buffers. If/when our hw gains support for +non-snooped pcie transactions then we must fix this mode at allocation time as +a new GEM extension. + +This is related to the mmap problem, because in general (meaning, when we're +not running on intel cpus) the cpu mmap must not, ever, be inconsistent with +allocation mode. + +Possible idea is to let the kernel picks the mmap mode for userspace from the +following table: + +smem-only: WB. Userspace does not need to call clflush. + +smem+lmem: We only ever allow a single mode, so simply allocate this as uncached +memory, and always give userspace a WC mapping. GPU still does snooped access +here(assuming we can't turn it off like on DG1), which is a bit inefficient. + +lmem only: always WC + +This means on discrete you only get a single mmap mode, all others must be +rejected. That's probably going to be a new default mode or something like +that. + +Links +===== +[1] https://patchwork.freedesktop.org/series/86798/ + +[2] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5599#note_553791 diff --git a/Documentation/gpu/rfc/index.rst b/Documentation/gpu/rfc/index.rst index a8621f7dab8b..05670442ca1b 100644 --- a/Documentation/gpu/rfc/index.rst +++ b/Documentation/gpu/rfc/index.rst @@ -15,3 +15,7 @@ host such documentation: * Once the code has landed move all the documentation to the right places in the main core, helper or driver sections. + +.. toctree:: + + i915_gem_lmem.rst -- 2.26.3

1 8

[PATCH v4 0/9] drm: Support simple-framebuffer devices and firmware fbs
by Thomas Zimmermann 29 Apr '21

29 Apr '21

This patchset adds support for simple-framebuffer platform devices and a handover mechanism for native drivers to take-over control of the hardware. The new driver, called simpledrm, binds to a simple-frambuffer platform device. The kernel's boot code creates such devices for firmware-provided framebuffers, such as EFI-GOP or VESA. Typically the BIOS, UEFI or boot loader sets up the framebuffers. Description via device tree is also an option. Simpledrm is small enough to be linked into the kernel. The driver's main purpose is to provide graphical output during the early phases of the boot process, before the native DRM drivers are available. Native drivers are typically loaded from an initrd ram disk. Occationally simpledrm can also serve as interim solution on graphics hardware without native DRM driver. So far distributions rely on fbdev drivers, such as efifb, vesafb or simplefb, for early-boot graphical output. However fbdev is deprecated and the drivers do not provide DRM interfaces for modern userspace. Patches 1 and 2 prepare the DRM format helpers for simpledrm. Patches 4 to 8 add the simpledrm driver. It's build on simple DRM helpers and SHMEM. It supports 16-bit, 24-bit and 32-bit RGB framebuffers. During pageflips, SHMEM buffers are copied into the framebuffer memory, similar to cirrus or mgag200. The code in patches 7 and 8 handles clocks and regulators. It's based on the simplefb drivers, but has been modified for DRM. Patches 3 and 9 add a hand-over mechanism. Simpledrm acquires it's framebuffer's I/O-memory range and can be hot-unplugged by a native driver. The native driver will remove simpledrm before taking over the hardware. The removal is integrated into existing helpers, so existing drivers use it automatically. I've also been working on fastboot support (i.e., flicker-free booting). This requires state-readout from simpledrm via generic interfaces, as outlined in [1]. I do have some prototype code, but it will take a while to get this ready. Simpledrm will then support it. I've tested simpledrm with x86 EFI and VESA framebuffers, which both work reliably. The fbdev console and Weston work automatically. Xorg requires manual configuration of the device. Xorgs current modesetting driver does not work with both, platform and PCI device, for the same physical hardware. Once configured, X11 works. I looked into X11, but couldn't see an easy way of fixing the problem. With the push towards Wayland+Xwayland I expect the problem to become a non-issue soon. Additional testing has been reported at [2]. One cosmetical issue is that simpledrm's device file is card0 and the native driver's device file is card1. After simpledrm has been kicked out, only card1 is left. This does not seem to be a practical problem however. TODO/IDEAS: * provide deferred takeover * provide bootsplash DRM client * make simplekms usable with ARM-EFI fbs v4: * provide interface for acquiring firmware framebuffers (Daniel) * make simpledrm and simplefb mutually exclusive (Maxime) * documentation fixes v3: * clear screen to black when disabled (Daniel) * rebase onto existing aperture helpers * detach via hot-unplug via platform_device_unregister() v2: * rename to simpledrm, aperture helpers * reorganized patches * use hotplug helpers for removal (Daniel) * added DT match tables (Rob) * use shadow-plane helpers * lots of minor cleanups [1] https://lore.kernel.org/dri-devel/CAKMK7uHtqHy_oz4W7F+hmp9iqp7W5Ra8CxPvJ=9B… [2] https://lore.kernel.org/dri-devel/1761762.3HQLrFs1K7@nerdopolis/ Thomas Zimmermann (9): drm/format-helper: Pass destination pitch to drm_fb_memcpy_dstclip() drm/format-helper: Add blitter functions drm/aperture: Add infrastructure for aperture ownership drm: Add simpledrm driver drm/simpledrm: Add fbdev emulation drm/simpledrm: Initialize framebuffer data from device-tree node drm/simpledrm: Acquire clocks from DT device node drm/simpledrm: Acquire regulators from DT device node drm/simpledrm: Acquire memory aperture for framebuffer Documentation/gpu/drm-internals.rst | 21 +- MAINTAINERS | 7 + drivers/gpu/drm/drm_aperture.c | 221 +++++- drivers/gpu/drm/drm_format_helper.c | 96 ++- drivers/gpu/drm/mgag200/mgag200_mode.c | 2 +- drivers/gpu/drm/tiny/Kconfig | 16 + drivers/gpu/drm/tiny/Makefile | 1 + drivers/gpu/drm/tiny/cirrus.c | 2 +- drivers/gpu/drm/tiny/simpledrm.c | 896 +++++++++++++++++++++++++ drivers/video/fbdev/Kconfig | 2 +- include/drm/drm_aperture.h | 20 +- include/drm/drm_format_helper.h | 10 +- 12 files changed, 1254 insertions(+), 40 deletions(-) create mode 100644 drivers/gpu/drm/tiny/simpledrm.c -- 2.31.1

5 20

[PATCH] drm/vc4: fix argument ordering in vc4_crtc_get_margins()
by Dan Carpenter 29 Apr '21

29 Apr '21

Cppcheck complains that the declaration doesn't match the function definition. Obviously "left" should come before "right". The caller and the function implementation are done this way, it's just the declaration which is wrong so this doesn't affect runtime. Reported-by: kernel test robot <lkp(a)intel.com> Signed-off-by: Dan Carpenter <dan.carpenter(a)oracle.com> --- drivers/gpu/drm/vc4/vc4_drv.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h index a7500716cf3f..5dceadc61600 100644 --- a/drivers/gpu/drm/vc4/vc4_drv.h +++ b/drivers/gpu/drm/vc4/vc4_drv.h @@ -825,7 +825,7 @@ void vc4_crtc_destroy_state(struct drm_crtc *crtc, void vc4_crtc_reset(struct drm_crtc *crtc); void vc4_crtc_handle_vblank(struct vc4_crtc *crtc); void vc4_crtc_get_margins(struct drm_crtc_state *state, - unsigned int *right, unsigned int *left, + unsigned int *left, unsigned int *right, unsigned int *top, unsigned int *bottom); /* vc4_debugfs.c */ -- 2.30.2

2 1

[PULL] drm-misc-next-fixes
by Maxime Ripard 29 Apr '21

29 Apr '21

Hi Dave, Daniel, Here's this week drm-misc-next-fixes PR, for the next merge window Thanks! Maxime drm-misc-next-fixes-2021-04-22: A few fixes for the next merge window, with some build fixes for anx7625 and lt8912b bridges, incorrect error handling for lt8912b and TTM, and one fix for TTM page limit accounting. The following changes since commit 9c0fed84d5750e1eea6c664e073ffa2534a17743: Merge tag 'drm-intel-next-2021-04-01' of git://anongit.freedesktop.org/drm/drm-intel into drm-next (2021-04-08 14:02:21 +1000) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-next-fixes-2021-04-22 for you to fetch changes up to a4394b6d0a273941a75ebe86a86d6416d536ed0f: drm/ttm: Don't count pages in SG BOs against pages_limit (2021-04-21 15:35:20 +0200) ---------------------------------------------------------------- A few fixes for the next merge window, with some build fixes for anx7625 and lt8912b bridges, incorrect error handling for lt8912b and TTM, and one fix for TTM page limit accounting. ---------------------------------------------------------------- Adrien Grassein (1): drm/bridge: lt8912b: fix incorrect handling of of_* return values Christian König (1): drm/ttm: fix return value check Felix Kuehling (1): drm/ttm: Don't count pages in SG BOs against pages_limit Randy Dunlap (2): drm: bridge: fix ANX7625 use of mipi_dsi_() functions drm: bridge: fix LONTIUM use of mipi_dsi_() functions drivers/gpu/drm/bridge/Kconfig | 3 +++ drivers/gpu/drm/bridge/analogix/Kconfig | 1 + drivers/gpu/drm/bridge/lontium-lt8912b.c | 32 +++++++++++++++++--------------- drivers/gpu/drm/ttm/ttm_tt.c | 29 +++++++++++++++++++---------- 4 files changed, 40 insertions(+), 25 deletions(-)

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dri-devel April 2021