March 2015 Archives by thread

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Starting: Sun Mar 1 07:09:23 PST 2015
Ending: Tue Mar 31 22:10:46 PDT 2015
Messages: 231

• [Beignet] [PATCH 2/3] Add llvm3.6 build support.   Steven Newbury
  • [Beignet] [PATCH 2/3] Add llvm3.6 build support.   Yang, Rong R
• [Beignet] [PATCH] GBE: remove the unecessary type check for SEL instructio.   Zhigang Gong
  • [Beignet] [PATCH] GBE: remove the unecessary type check for SEL instructio.   Song, Ruiling
• [Beignet] [PATCH] GBE: support compare two bool variables.   Zhigang Gong
  • [Beignet] [PATCH] GBE: support compare two bool variables.   Yang, Rong R
    • [Beignet] [PATCH] GBE: support compare two bool variables.   Gong, Zhigang
      • [Beignet] [PATCH] GBE: support compare two bool variables.   Yang, Rong R
• [Beignet] [PATCH] GBE: add fastcall support.   Zhigang Gong
  • [Beignet] [PATCH] GBE: add fastcall support.   Yang, Rong R
• [Beignet] [PATCH] Build: use -Bsymbolic to fix conflicts with other LLVM users.   Yang, Rong R
• [Beignet] [PATCH] drm/i915: Export total subslice and EU counts   jeff.mcgee at intel.com
  • [Beignet] [PATCH] drm/i915: Export total subslice and EU counts   Jeff McGee
  • [Beignet] [PATCH] drm/i915: Export total subslice and EU counts   Daniel Vetter
    • [Beignet] [PATCH] drm/i915: Export total subslice and EU counts   Daniel Vetter
  • [Beignet] [PATCH] drm/i915: Export total subslice and EU counts   Zhigang Gong
    • [Beignet] [PATCH] drm/i915: Export total subslice and EU counts   Jeff McGee
      • [Beignet] [PATCH] drm/i915: Export total subslice and EU counts   Zhigang Gong
      • [Beignet] [PATCH] drm/i915: Export total subslice and EU counts   Daniel Vetter
    • [Beignet] [PATCH] drm/i915: Export total subslice and EU counts   Jeff McGee
  • [Beignet] [PATCH v2] drm/i915: Export total subslice and EU counts   jeff.mcgee at intel.com
• [Beignet] [PATCH] intel: Export total subslice and EU counts   jeff.mcgee at intel.com
  • [Beignet] [PATCH 1/2 v2] intel: Export total subslice and EU counts   jeff.mcgee at intel.com
    • [Beignet] [PATCH 2/2] configure.ac: bump version to 2.4.60 for release   jeff.mcgee at intel.com
    • [Beignet] [Intel-gfx] [PATCH 1/2 v2] intel: Export total subslice and EU counts   Damien Lespiau
  • [Beignet] [PATCH] intel: Export total subslice and EU counts   Damien Lespiau
• [Beignet] [PATCH] tests/core_getparams: Create new test core_getparams   jeff.mcgee at intel.com
  • [Beignet] [PATCH i-g-t 1/2] tests/core_getparams: Create new test core_getparams   jeff.mcgee at intel.com
    • [Beignet] [PATCH i-g-t 2/2] configure: Bump required libdrm version to 2.4.60   jeff.mcgee at intel.com
    • [Beignet] [PATCH i-g-t 2/2] configure: Bump required libdrm version to 2.4.60   jeff.mcgee at intel.com
    • [Beignet] [PATCH i-g-t 2/2] configure: Bump required libdrm version to 2.4.60   jeff.mcgee at intel.com
      • [Beignet] [Intel-gfx] [PATCH i-g-t 2/2] configure: Bump required libdrm version to 2.4.60   Daniel Vetter
      • [Beignet] [Intel-gfx] [PATCH i-g-t 2/2] configure: Bump required libdrm version to 2.4.60   Jeff McGee
      • [Beignet] [Intel-gfx] [PATCH i-g-t 2/2] configure: Bump required libdrm version to 2.4.60   Rob Clark
      • [Beignet] [Intel-gfx] [PATCH i-g-t 2/2] configure: Bump required libdrm version to 2.4.60   Jeff McGee
      • [Beignet] [Intel-gfx] [PATCH i-g-t 2/2] configure: Bump required libdrm version to 2.4.60   Rob Clark
      • [Beignet] [Intel-gfx] [PATCH i-g-t 2/2] configure: Bump required libdrm version to 2.4.60   Daniel Vetter
      • [Beignet] [Intel-gfx] [PATCH i-g-t 2/2] configure: Bump required libdrm version to 2.4.60   Jeff McGee
      • [Beignet] [Intel-gfx] [PATCH i-g-t 2/2] configure: Bump required libdrm version to 2.4.60   Daniel Vetter
      • [Beignet] [Intel-gfx] [PATCH i-g-t 2/2] configure: Bump required libdrm version to 2.4.60   Jeff McGee
    • [Beignet] [PATCH i-g-t v2] tests/core_getparams: Create new test core_getparams   jeff.mcgee at intel.com
      • [Beignet] [PATCH i-g-t v3] tests/core_getparams: Create new test core_getparams   jeff.mcgee at intel.com
      • [Beignet] [PATCH i-g-t v3] tests/core_getparams: Create new test core_getparams   Daniel Vetter
      • [Beignet] [Intel-gfx] [PATCH i-g-t v3] tests/core_getparams: Create new test core_getparams   Zhigang Gong
      • [Beignet] [Intel-gfx] [PATCH i-g-t v3] tests/core_getparams: Create new test core_getparams   Daniel Vetter
      • [Beignet] [Intel-gfx] [PATCH i-g-t v3] tests/core_getparams: Create new test core_getparams   Jeff McGee
      • [Beignet] [Intel-gfx] [PATCH i-g-t v3] tests/core_getparams: Create new test core_getparams   Daniel Vetter
      • [Beignet] [Intel-gfx] [PATCH i-g-t v3] tests/core_getparams: Create new test core_getparams   Jeff McGee
• [Beignet] [PATCH 1/2] Add driver callback for updating device info   jeff.mcgee at intel.com
  • [Beignet] [PATCH 2/2] Query the driver directly for compute units and subslice   jeff.mcgee at intel.com
    • [Beignet] [PATCH 2/2 v2] Query the driver directly for compute units and subslice   jeff.mcgee at intel.com
      • [Beignet] [PATCH 2/2 v2] Query the driver directly for compute units and subslice   Zhigang Gong
      • [Beignet] [PATCH 2/2 v2] Query the driver directly for compute units and subslice   Jeff McGee
  • [Beignet] [PATCH 1/2] Add driver callback for updating device info   Zhigang Gong
• [Beignet] [PATCH] Fix llvm3.6 build error.   Yang Rong
  • [Beignet] [PATCH] Fix llvm3.6 build error.   Song, Ruiling
• [Beignet] [PATCH 1/6] Add the indirect fields and functions for gen register.   junyan.he at inbox.com
• [Beignet] [PATCH 2/6] Delete bswap logic in the llvm_to_gen stage.   junyan.he at inbox.com
• [Beignet] [PATCH 3/6] Add functions to set a0 register.   junyan.he at inbox.com
• [Beignet] [PATCH 4/6] Correct indirect mode encoder setting for Gen7   junyan.he at inbox.com
• [Beignet] [PATCH 5/6] Handle the bswap using indirect mode access.   junyan.he at inbox.com
• [Beignet] [PATCH 6/6] Modify the bswap test case.   junyan.he at inbox.com
• [Beignet] Preventing zero GPU virtual address allocation   Song, Ruiling
  • [Beignet] [Intel-gfx] Preventing zero GPU virtual address allocation   Daniel Vetter
    • [Beignet] [Intel-gfx] Preventing zero GPU virtual address allocation   Chris Wilson
    • [Beignet] [Intel-gfx] Preventing zero GPU virtual address allocation   Daniel Vetter
      • [Beignet] [Intel-gfx] Preventing zero GPU virtual address allocation   Chris Wilson
      • [Beignet] [Intel-gfx] Preventing zero GPU virtual address allocation   Jesse Barnes
      • [Beignet] [Intel-gfx] Preventing zero GPU virtual address allocation   Jesse Barnes
      • [Beignet] [Intel-gfx] Preventing zero GPU virtual address allocation   Zou, Nanhai
      • [Beignet] [Intel-gfx] Preventing zero GPU virtual address allocation   Chris Wilson
      • [Beignet] [Intel-gfx] Preventing zero GPU virtual address allocation   Zou, Nanhai
      • [Beignet] [Intel-gfx] Preventing zero GPU virtual address allocation   Chris Wilson
      • [Beignet] [Intel-gfx] Preventing zero GPU virtual address allocation   Zou, Nanhai
      • [Beignet] [Intel-gfx] Preventing zero GPU virtual address allocation   David Weinehall
      • [Beignet] [Intel-gfx] Preventing zero GPU virtual address allocation   Chris Wilson
      • [Beignet] [Intel-gfx] Preventing zero GPU virtual address allocation   Daniel Vetter
      • [Beignet] [Intel-gfx] Preventing zero GPU virtual address allocation   Chris Wilson
      • [Beignet] [Intel-gfx] Preventing zero GPU virtual address allocation   Daniel Vetter
      • [Beignet] [Intel-gfx] Preventing zero GPU virtual address allocation   Chris Wilson
      • [Beignet] [Intel-gfx] Preventing zero GPU virtual address allocation   Daniel Vetter
      • [Beignet] [Intel-gfx] Preventing zero GPU virtual address allocation   Song, Ruiling
      • [Beignet] [Intel-gfx] Preventing zero GPU virtual address allocation   Daniel Vetter
      • [Beignet] [Intel-gfx] Preventing zero GPU virtual address allocation   Jesse Barnes
      • [Beignet] [Intel-gfx] Preventing zero GPU virtual address allocation   Zhigang Gong
      • [Beignet] [Intel-gfx] Preventing zero GPU virtual address allocation   Zou, Nanhai
      • [Beignet] [Intel-gfx] Preventing zero GPU virtual address allocation   Jesse Barnes
      • [Beignet] [Intel-gfx] Preventing zero GPU virtual address allocation   Song, Ruiling
      • [Beignet] [Intel-gfx] Preventing zero GPU virtual address allocation   David Weinehall
      • [Beignet] [Intel-gfx] Preventing zero GPU virtual address allocation   Daniel Vetter
      • [Beignet] [Intel-gfx] Preventing zero GPU virtual address allocation   Song, Ruiling
      • [Beignet] [Intel-gfx] Preventing zero GPU virtual address allocation   Daniel Vetter
      • [Beignet] [Intel-gfx] Preventing zero GPU virtual address allocation   Jesse Barnes
• [Beignet] double precision support   Malcolm Roberts
  • [Beignet] double precision support   Zhigang Gong
    • [Beignet] double precision support   Matt Turner
      • [Beignet] double precision support   Zhigang Gong
• [Beignet] [PATCH 1/7] Backend: Add the indirect fields and functions for gen register.   junyan.he at inbox.com
• [Beignet] [V2 PATCH 1/7] Backend: Add the indirect fields and functions for gen register.   junyan.he at inbox.com
• [Beignet] [V2 PATCH 2/7] Backend: Add functions to set a0 register.   junyan.he at inbox.com
• [Beignet] [V2 PATCH 3/7] Backend: Correct indirect mode encoder setting for Gen7.   junyan.he at inbox.com
• [Beignet] [V2 PATCH 4/7] Backend: Correct indirect mode encoder setting for Gen8.   junyan.he at inbox.com
• [Beignet] [V2 PATCH 5/7] Backend: Handle the bswap using indirect mode access.   junyan.he at inbox.com
  • [Beignet] [V2 PATCH 5/7] Backend: Handle the bswap using indirect mode access.   Zhigang Gong
    • [Beignet] [V2 PATCH 5/7] Backend: Handle the bswap using indirect mode access.   He Junyan
      • [Beignet] [V2 PATCH 5/7] Backend: Handle the bswap using indirect mode access.   Zhigang Gong
• [Beignet] [V2 PATCH 6/7] Backend: Delete bswap logic in the llvm_to_gen stage.   junyan.he at inbox.com
• [Beignet] [V2 PATCH 7/7] utest: Update the test case for bswap.   junyan.he at inbox.com
• [Beignet] [PATCH] GBE: add a new incompatible compile option -cl-finite-math-only.   Zhigang Gong
• [Beignet] [PATCH 1/4] enable cl_khr_spir extension to build and run from SPIR binary.   xionghu.luo at intel.com
  • [Beignet] [PATCH 2/4] change the workitem related api to OVERLOABABLE.   xionghu.luo at intel.com
    • [Beignet] [PATCH 2/4] change the workitem related api to OVERLOABABLE.   Zhigang Gong
  • [Beignet] [PATCH 3/4] SPIR binary support for printf function.   xionghu.luo at intel.com
  • [Beignet] [PATCH 4/4] add utest for load spir binary.   xionghu.luo at intel.com
• [Beignet] [PATCH 1/9 V3] Backend: Add the indirect fields and functions for gen register.   junyan.he at inbox.com
  • [Beignet] [PATCH 1/9 V3] Backend: Add the indirect fields and functions for gen register.   Zhigang Gong
• [Beignet] [PATCH 2/9 V3] Backend: Add functions to set a0 register.   junyan.he at inbox.com
• [Beignet] [PATCH 3/9 V3] Backend: Correct indirect mode encoder setting for Gen7.   junyan.he at inbox.com
• [Beignet] [PATCH 4/9 V3] Backend: Correct indirect mode encoder setting for Gen8.   junyan.he at inbox.com
• [Beignet] [PATCH 5/9 V3] Backend: Handle the bswap using indirect mode access.   junyan.he at inbox.com
• [Beignet] [PATCH 6/9 V3] Backend: Handle the bswap using indirect mode access.   junyan.he at inbox.com
• [Beignet] [PATCH 7/9 V3] Add a0 setting and bswap logic for GEN8   junyan.he at inbox.com
• [Beignet] [PATCH 8/9 V3] Backend: Delete bswap logic in the llvm_to_gen stage.   junyan.he at inbox.com
• [Beignet] [PATCH 9/9 V3] Modify the utest case for bswap.   junyan.he at inbox.com
• [Beignet] [PATCH 1/7] replace fabs with llvm intrinsic.   xionghu.luo at intel.com
  • [Beignet] [PATCH 2/7] replace rndz with llvm intrinsic.   xionghu.luo at intel.com
  • [Beignet] [PATCH 3/7] replace rnde with llvm intrinsic.   xionghu.luo at intel.com
  • [Beignet] [PATCH 4/7] replace rndu with llvm intrinsic.   xionghu.luo at intel.com
  • [Beignet] [PATCH 5/7] replace rndd with llvm intrinsic.   xionghu.luo at intel.com
  • [Beignet] [PATCH 6/7] replace mad with llvm intrinsic.   xionghu.luo at intel.com
    • [Beignet] [PATCH 6/7] replace mad with llvm intrinsic.   Matt Turner
      • [Beignet] [PATCH 6/7] replace mad with llvm intrinsic.   Song, Ruiling
      • [Beignet] [PATCH 6/7] replace mad with llvm intrinsic.   Matt Turner
      • [Beignet] [PATCH 6/7] replace mad with llvm intrinsic.   Song, Ruiling
      • [Beignet] [PATCH 6/7] replace mad with llvm intrinsic.   Song, Ruiling
      • [Beignet] [PATCH 6/7] replace mad with llvm intrinsic.   Song, Ruiling
  • [Beignet] [PATCH 7/7] replace pow with llvm intrinsic.   xionghu.luo at intel.com
  • [Beignet] [PATCH 1/7] replace fabs with llvm intrinsic.   Zhigang Gong
• [Beignet] [PATCH 1/2] Backend: Add the logic to handle uniform src for BSwap Gen8.   junyan.he at inbox.com
  • [Beignet] [PATCH 1/2] Backend: Add the logic to handle uniform src for BSwap Gen8.   Zhigang Gong
• [Beignet] [PATCH 2/2] Backend: Fix errors in disasm for indirect instruction Gen8.   junyan.he at inbox.com
• [Beignet] [PATCH] Add example to show v4l2 buffer sharing with extension clGetMemObjectFdIntel.   Chuanbo Weng
• [Beignet] [PATCH] GBE: Only emit multiply when immediate is not one.   Ruiling Song
  • [Beignet] [PATCH] GBE: Only emit multiply when immediate is not one.   Zhigang Gong
• [Beignet] [Intel-gfx] [PATCH] drm/i915: Add soft-pinning API for execbuffer   Zhenyu Wang
• [Beignet] [PATCH] diasble the SPIR case for llvm before than 3.3.   xionghu.luo at intel.com
  • [Beignet] [PATCH] diasble the SPIR case for llvm before than 3.3.   Zhigang Gong
• [Beignet] [PATCH 1/3] reset the SPIR target datalayout.   xionghu.luo at intel.com
• [Beignet] [PATCH V2 1/3] reset the SPIR target datalayout.   xionghu.luo at intel.com
  • [Beignet] [PATCH V2 2/3] only support spir extension for beignet build with llvm 3.5 or later.   xionghu.luo at intel.com
  • [Beignet] [PATCH V2 3/3] simple return if spir extension not supported.   xionghu.luo at intel.com
  • [Beignet] [PATCH V2 1/3] reset the SPIR target datalayout.   Zhigang Gong
• [Beignet] [PATCH] GBE: fix an image related bugs.   Zhigang Gong
  • [Beignet] [PATCH] GBE: fix an image related bugs.   Yang, Rong R
• [Beignet] [ANNOUNCE] Beignet 1.0.2 (2015-03-16)   Zhigang Gong
• [Beignet] wrong CMAKE_LIBRARY_ARCHITECTURE on x86_64   Igor Gnatenko
  • [Beignet] wrong CMAKE_LIBRARY_ARCHITECTURE on x86_64   Zhigang Gong
    • [Beignet] wrong CMAKE_LIBRARY_ARCHITECTURE on x86_64   Igor Gnatenko
      • [Beignet] wrong CMAKE_LIBRARY_ARCHITECTURE on x86_64   Zhigang Gong
    • [Beignet] wrong CMAKE_LIBRARY_ARCHITECTURE on x86_64   Rebecca N. Palmer
      • [Beignet] wrong CMAKE_LIBRARY_ARCHITECTURE on x86_64   Zhigang Gong
• [Beignet] [PATCH] Add LLVM_INCLUDE_DIR to CMakeList of src.   junyan.he at inbox.com
  • [Beignet] [PATCH] Add LLVM_INCLUDE_DIR to CMakeList of src.   Zhigang Gong
• [Beignet] [PATCH] Build: fix the beignet icd name when CMAKE_INSTALL_FULL_LIBDIR is undefined.   Zhigang Gong
• [Beignet] [PATCH] strip PointerCast for call instructions before use.   xionghu.luo at intel.com
• [Beignet] [patch v2] strip PointerCast for call instructions before use.   xionghu.luo at intel.com
  • [Beignet] [patch v2] strip PointerCast for call instructions before use.   Guo, Yejun
  • [Beignet] [patch v2] strip PointerCast for call instructions before use.   Zhigang Gong
• [Beignet] [PATCH] correct env var to output llvm IR   Guo Yejun
  • [Beignet] [PATCH] correct env var to output llvm IR   Zhigang Gong
• [Beignet] [PATCH] Generate NAN for UNDEF value in printf parser.   junyan.he at inbox.com
  • [Beignet] [PATCH] Generate NAN for UNDEF value in printf parser.   Zhigang Gong
• [Beignet] [PATCH] runtime: fix a conformance bug in cl_get_kernel_arg_info.   Zhigang Gong
  • [Beignet] [PATCH] runtime: fix a conformance bug in cl_get_kernel_arg_info.   Weng, Chuanbo
• [Beignet] [PATCH 1/2] [opencl-2.0] clCreateSampler replaced by clCreateSamplerWithProperties.   xionghu.luo at intel.com
  • [Beignet] [PATCH 2/2] [opencl-2.0] sampler API upgrade for utest.   xionghu.luo at intel.com
• [Beignet] [PATCH] BUGFIX: Prohibit 'make package' from doing system install of ICD vendor file   Brian Kloppenborg
  • [Beignet] [PATCH] BUGFIX: Prohibit 'make package' from doing system install of ICD vendor file   Zhigang Gong
    • [Beignet] [PATCH] BUGFIX: Prohibit 'make package' from doing system install of ICD vendor file   Brian Kloppenborg
• [Beignet] [PATCH] Fix: Event callback that not executed when command already marked CL_COMPLETE   David Couturier
  • [Beignet] [PATCH] Fix: Event callback that not executed when command already marked CL_COMPLETE   Yang, Rong R
    • [Beignet] [PATCH] Fix: Event callback that not executed when command already marked CL_COMPLETE   David Couturier
      • [Beignet] [PATCH] Fix: Event callback that not executed when command already marked CL_COMPLETE   Yang, Rong R
      • [Beignet] [PATCH] Fix: Event callback that not executed when command already marked CL_COMPLETE   Zhigang Gong
• [Beignet] [PATCH 1/2] add 3 simd level built-in functions: shuffle, simdsize and simdid   Guo Yejun
  • [Beignet] [PATCH 1/2] add 3 simd level built-in functions: shuffle, simdsize and simdid   Guo, Yejun
• [Beignet] [PATCH 2/2] add utest for __gen_ocl_simd_shuffle and __gen_ocl_get_simd_size/id   Guo Yejun
• [Beignet] [PATCH] Use matching versions of clang/llvm and libclang/libllvm   Rebecca N. Palmer
  • [Beignet] [PATCH] Use matching versions of clang/llvm and libclang/libllvm   Zhigang Gong
• [Beignet] FindLLVM: allow LLVM/Clang 3.6   Rebecca N. Palmer
  • [Beignet] FindLLVM: allow LLVM/Clang 3.6   Zhigang Gong
• [Beignet] [PATCH] Don't crash if device inaccessible   Rebecca N. Palmer
  • [Beignet] [PATCH] Don't crash if device inaccessible   Zhigang Gong
• [Beignet] Intermittent runtime_marker_list() test failure   Rebecca N. Palmer
• [Beignet] [PATCH] BDW: Refine I64HADD and I64RHADD.   Yang Rong
  • [Beignet] [PATCH] BDW: Refine I64HADD and I64RHADD.   Song, Ruiling
    • [Beignet] [PATCH] BDW: Refine I64HADD and I64RHADD.   He Junyan
• [Beignet] [PATCH OpenCL 2.0] libocl: Add the module for work_group functions.   junyan.he at inbox.com
• [Beignet] [Patch V2] BDW: Refine I64HADD and I64RHADD.   Yang Rong
  • [Beignet] [Patch V2] BDW: Refine I64HADD and I64RHADD.   He Junyan
• [Beignet] [PATCH] Fix: Event callback that were not executed when command was already CL_COMPLETE + thread safety for callbacks   David Couturier
  • [Beignet] [PATCH] Fix: Event callback that were not executed when command was already CL_COMPLETE + thread safety for callbacks   Yang, Rong R
• [Beignet] [PATCH OpenCL 2.0] Backend: Update the workgroup instructions for llvm backend to gen.   junyan.he at inbox.com
  • [Beignet] [PATCH OpenCL 2.0] Backend: Update the workgroup instructions for llvm backend to gen.   Yang, Rong R
• [Beignet] [PATCH] Fix: (v3) Event callback that were not executed when command was already CL_COMPLETE + thread safety for callbacks   David Couturier
  • [Beignet] [PATCH] Fix: (v3) Event callback that were not executed when command was already CL_COMPLETE + thread safety for callbacks   Yang, Rong R
• [Beignet] [PATCH v2 0/3] Patchset of v4l2 buffer sharing.   Chuanbo Weng
• [Beignet] [PATCH v2 1/3] Add extension clCloseMemObjectFdIntel().   Chuanbo Weng
  • [Beignet] [PATCH v2 1/3] Add extension clCloseMemObjectFdIntel().   Yuan, Feng
• [Beignet] [PATCH v2 2/3] Add example to show v4l2 buffer sharing with extension clGetMemObjectFdIntel and clCloseMemObjectFdIntel.   Chuanbo Weng
• [Beignet] [PATCH v2 3/3] Add document to describe the detials of v4l2 buffer sharing.   Chuanbo Weng
• [Beignet] [PATCH] BDW: Refine unpacked_ud in the gen8_context.cpp.   Yang Rong
• [Beignet] [PATCH 1/2] CHV: Add cherryview support in the runtime.   Yang Rong
  • [Beignet] [PATCH 2/2] Chv: Add chv backend support.   Yang Rong
• [Beignet] [PATCH] Fix a segmentation fault.   Yang Rong
• [Beignet] [PATCH 1/3] add benckmark for copy data from buffer to image.   xionghu.luo at intel.com
  • [Beignet] [PATCH 2/3] Optimization of clEnqueueCopyBufferToImage for 16 aligned case.   xionghu.luo at intel.com
    • [Beignet] [PATCH 2/3] Optimization of clEnqueueCopyBufferToImage for 16 aligned case.   Weng, Chuanbo
  • [Beignet] [PATCH 3/3] Add missing code.   xionghu.luo at intel.com
  • [Beignet] [PATCH 1/3] add benckmark for copy data from buffer to image.   Luo, Xionghu
    • [Beignet] [PATCH 1/3] add benckmark for copy data from buffer to image.   Weng, Chuanbo
• [Beignet] [PATCH 1/8] strip unsupported attributes and calling conventions.   Zhigang Gong
  • [Beignet] [PATCH 2/8] GBE: fix safe type definition.   Zhigang Gong
  • [Beignet] [PATCH 3/8] GBE: extend registers/tuples/immediates to 32bit wide.   Zhigang Gong
  • [Beignet] [PATCH 4/8] GBE: extend backend label to 32 bit.   Zhigang Gong
  • [Beignet] [PATCH 5/8] GBE: don't type cast register/labelindex to integer.   Zhigang Gong
  • [Beignet] [PATCH 6/8] GBE: Extend front label ip to 32 bit on demand.   Zhigang Gong
  • [Beignet] [PATCH 7/8] GBE: Use actual bti information to determine a pointer's addressspace.   Zhigang Gong
  • [Beignet] [PATCH 8/8] GBE: refine error handling for private libva buffer sharing extension.   Zhigang Gong
• [Beignet] [patch v2 1/2] Optimization of clEnqueueCopyBufferToImage for 16 aligned case.   xionghu.luo at intel.com
  • [Beignet] [patch v2 2/2] add benckmark for copy data from buffer to image.   xionghu.luo at intel.com

Last message date: Tue Mar 31 22:10:46 PDT 2015
Archived on: Tue Mar 31 22:10:34 PDT 2015

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